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Subject: Re: [RFC PATCH 3/7] arm64: mm: use nGnRnE instead of nGnRE on Apple
 processors
To:     Mohamed Mediouni <mohamed.mediouni@caramail.com>
CC:     <linux-arm-kernel@lists.infradead.org>,
        Catalin Marinas <catalin.marinas@arm.com>,
        Will Deacon <will@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Marc Zyngier <maz@kernel.org>,
        Hector Martin <marcan@marcan.st>,
        <linux-kernel@vger.kernel.org>, Stan Skowronek <stan@corellium.com>
References: <20210120132717.395873-1-mohamed.mediouni@caramail.com>
 <20210120132717.395873-4-mohamed.mediouni@caramail.com>
 <ce5692a9-e716-514a-f196-b0645bb03eb8@amazon.com>
 <17579DC5-13AF-48E1-9B72-91B14AB485FA@caramail.com>
From:   Alexander Graf <graf@amazon.com>
Message-ID: <6047872c-8a40-4159-aeb6-ea439bfafd82@amazon.com>
Date:   Wed, 20 Jan 2021 19:10:33 +0100
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On 20.01.21 19:06, Mohamed Mediouni wrote:
> =

>> On 20 Jan 2021, at 17:47, Alexander Graf <graf@amazon.com> wrote:
>>
>> On 20.01.21 14:27, Mohamed Mediouni wrote:
>>> Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious hardw=
are quirk.
>>> On Apple processors, writes using the nGnRE device memory type get drop=
ped in flight,
>>> getting to nowhere.
>>> Signed-off-by: Stan Skowronek <stan@corellium.com>
>>> Signed-off-by: Mohamed Mediouni <mohamed.mediouni@caramail.com>
>>> ---
>>>   arch/arm64/mm/proc.S | 26 ++++++++++++++++++++++++++
>>>   1 file changed, 26 insertions(+)
>>> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
>>> index 1f7ee8c8b7b8..06436916f137 100644
>>> --- a/arch/arm64/mm/proc.S
>>> +++ b/arch/arm64/mm/proc.S
>>> @@ -51,6 +51,25 @@
>>>   #define TCR_KASAN_HW_FLAGS 0
>>>   #endif
>>> +#ifdef CONFIG_ARCH_APPLE
>>
>> Is there any particular reason for this #ifdef?
>>
>>
>> Alex
>>
> Not a particular reason, as we explicitly check for the implementer ID. H=
owever,
> without CONFIG_ARCH_APPLE, other parts of the support for Apple CPUs
> will not be available anyway.

The ifdef below for code looks ok to me, I'm explicitly wondering why =

you're guarding the #define :)

Alex

>>> +
>>> +/*
>>> + * Apple cores appear to black-hole writes done with nGnRE.
>>> + * We settled on a work-around that uses MAIR vs changing every single=
 user of
>>> + * nGnRE across the arm64 code.
>>> + */
>>> +
>>> +#define MAIR_EL1_SET_APPLE                                          \
>>> +    (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) |      \
>>> +     MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRE) |       \
>>> +     MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) |            \
>>> +     MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) |              \
>>> +     MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) |                    \
>>> +     MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) |              \
>>> +     MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED))
>>> +
>>> +#endif
>>> +
>>>   /*
>>>    * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal m=
emory and
>>>    * changed during __cpu_setup to Normal Tagged if the system supports=
 MTE.
>>> @@ -432,6 +451,13 @@ SYM_FUNC_START(__cpu_setup)
>>>        * Memory region attributes
>>>        */
>>>       mov_q   x5, MAIR_EL1_SET
>>> +#ifdef CONFIG_ARCH_APPLE
>>> +    mrs     x0, MIDR_EL1
>>> +    lsr     w0, w0, #24
>>> +    mov_q   x1, MAIR_EL1_SET_APPLE
>>> +    cmp     x0, #0x61                       // 0x61 =3D Implementer: A=
pple
>>> +    csel    x5, x1, x5, eq
>>> +#endif
>>>   #ifdef CONFIG_ARM64_MTE
>>>       mte_tcr .req    x20
>>> --
>>> 2.29.2


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