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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id x12sm423724oic.51.2021.01.20.07.50.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Jan 2021 07:50:19 -0800 (PST) Received: (nullmailer pid 214205 invoked by uid 1000); Wed, 20 Jan 2021 15:50:18 -0000 Date: Wed, 20 Jan 2021 09:50:18 -0600 From: Rob Herring To: Manivannan Sadhasivam Cc: bjorn.andersson@linaro.org, sboyd@kernel.org, jassisinghbrar@gmail.com, viresh.kumar@linaro.org, linux-clk@vger.kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, linux-kernel@vger.kernel.org, agross@kernel.org, ulf.hansson@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 3/5] dt-bindings: clock: Add Qualcomm A7 PLL binding Message-ID: <20210120155018.GA213895@robh.at.kernel.org> References: <20210118041156.50016-1-manivannan.sadhasivam@linaro.org> <20210118041156.50016-4-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210118041156.50016-4-manivannan.sadhasivam@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 18 Jan 2021 09:41:54 +0530, Manivannan Sadhasivam wrote: > Add devicetree YAML binding for Cortex A7 PLL clock in Qualcomm > platforms like SDX55. > > Signed-off-by: Manivannan Sadhasivam > --- > .../devicetree/bindings/clock/qcom,a7pll.yaml | 51 +++++++++++++++++++ > 1 file changed, 51 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,a7pll.yaml > Please add Acked-by/Reviewed-by tags when posting new versions. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for acks received on the version they apply. If a tag was not added on purpose, please state why and what changed.