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Subject: Re: [PATCH V1] clk: qcom: gcc-sc7180: Mark the MM XO clocks to be always ON
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     Rajendra Nayak <rnayak@codeaurora.org>,
        linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
To:     AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@somainline.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Taniya Das <tdas@codeaurora.org>
Date:   Wed, 20 Jan 2021 18:46:03 -0800
Message-ID: <161119716362.3661239.18168143877101107424@swboyd.mtv.corp.google.com>
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Quoting AngeloGioacchino Del Regno (2021-01-20 01:16:17)
> Il 20/01/21 08:47, Taniya Das ha scritto:
> > There are intermittent GDSC power-up failures observed for titan top
> > gdsc, which requires the XO clock. Thus mark all the MM XO clocks always
> > enabled from probe.
> >=20
>=20
> Hello Tanya,
>=20
> > Fixes: 8d4025943e13 ("clk: qcom: camcc-sc7180: Use runtime PM ops inste=
ad of clk ones")
> > Signed-off-by: Taniya Das <tdas@codeaurora.org>
> > ---
> >   drivers/clk/qcom/gcc-sc7180.c | 47 ++++------------------------------=
---------
> >   1 file changed, 4 insertions(+), 43 deletions(-)
> >=20
> > --
> > Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
> > of the Code Aurora Forum, hosted by the  Linux Foundation.
> >=20
> > diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc718=
0.c
> > index b05901b..88e896a 100644
> > --- a/drivers/clk/qcom/gcc-sc7180.c
> > +++ b/drivers/clk/qcom/gcc-sc7180.c
> > @@ -1,6 +1,6 @@
> >   // SPDX-License-Identifier: GPL-2.0-only
> >   /*
> > - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
> > + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
> >    */
> >=20
> >   #include <linux/clk-provider.h>
> > @@ -919,19 +919,6 @@ static struct clk_branch gcc_camera_throttle_hf_ax=
i_clk =3D {
> >       },
> >   };
> >=20
> > -static struct clk_branch gcc_camera_xo_clk =3D {
> > -     .halt_reg =3D 0xb02c,
> > -     .halt_check =3D BRANCH_HALT,
> > -     .clkr =3D {
> > -             .enable_reg =3D 0xb02c,
> > -             .enable_mask =3D BIT(0),
> > -             .hw.init =3D &(struct clk_init_data){
> > -                     .name =3D "gcc_camera_xo_clk",
> > -                     .ops =3D &clk_branch2_ops,
> > -             },
> > -     },
> > -};
> > -
>=20
> Why are you avoiding to register these clocks entirely?
> If this is needed by the Titan GDSC, this clock "does indeed exist".
>=20
> If these clocks shall never be turned off, then you should add the
> CLK_IS_CRITICAL flag and perhaps add a comment explaining why.

I'd rather not have critical clks wasting kernel memory and registration
time if they're never going to be turned off and we're basically just
writing a bit so that they're always on. This patch looks OK to me from
that perspective. There aren't any parents for these clks either so
really it's a glorified bit toggle and poll to make sure that it is
enabled. Maybe we should be checking that they're actually enabled at
the end of probe, but otherwise we don't need all this complexity.