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[23.128.96.18]) by mx.google.com with ESMTP id u20si1781234edv.129.2021.01.21.01.00.27; Thu, 21 Jan 2021 01:00:52 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b="Dmmxrw/E"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726236AbhAUI4x (ORCPT + 99 others); Thu, 21 Jan 2021 03:56:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728259AbhAUI4Z (ORCPT ); Thu, 21 Jan 2021 03:56:25 -0500 Received: from mail-vs1-xe32.google.com (mail-vs1-xe32.google.com [IPv6:2607:f8b0:4864:20::e32]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B79D2C0613C1 for ; Thu, 21 Jan 2021 00:55:37 -0800 (PST) Received: by mail-vs1-xe32.google.com with SMTP id n18so630721vsa.12 for ; Thu, 21 Jan 2021 00:55:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ePsu1N7aD3BdUwzr3RcjhQbXEG8+bIemaO7C4xKDs2A=; b=Dmmxrw/ElDqEXAM9Qtq+V/hu48fzs4rvxkyHyBHsg45ozoS55ZMz39ndyE2rKMYvAP N07ZymUbewZ7oqS+k4b1OKgosrOcBt5tUvJmz3bGXcij1HIswjtnsx4oy9gj5F+oG+uf 45qKAXJvn/b6l6sI7xXAItrPqGrSYDURu7VYc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ePsu1N7aD3BdUwzr3RcjhQbXEG8+bIemaO7C4xKDs2A=; b=HTH0EoYG/R2VMLvIIr7RDJSr09g6ut2VgV3zRqllrrBQeSdGqUqjkL2uBsXgPgMfC1 Q2+yCFmZ3fasWer/stcrAhaS+scZyiNZ3ZzP/rHloZjWbW+Opwh4ty5KaaYqV84jARZ2 fCYzWMJaR2hec9UELPUomaDmn/ynC6VRITjRNpJ2OUMaPGlQMun+3RYMtahkF2AtXn4s DwKV9rnqHgQbSI+/2jgfpMkgKzymdmrpD/tW74tKCmL0s772Baz2M3sj+HNAn+fqIWQP f1l/H/WxsB7xb5iBKp7F9Y/QM/YzLwlRZOq0wIUsVpPgYsqzawrDd2YZrWlasp841yl0 eDsQ== X-Gm-Message-State: AOAM531xFKVM1jVun7QYkwMlBjtHm6CyQjXSJG1TPWGqvmDBPcpYqO5S KWyf7LAcRt2PS53DXNpLZn+kVGMEzD23TbBf5RDKlQ== X-Received: by 2002:a05:6102:34f:: with SMTP id e15mr9659982vsa.21.1611219336958; Thu, 21 Jan 2021 00:55:36 -0800 (PST) MIME-Version: 1.0 References: <20210121075149.1310-1-hailong.fan@mediatek.com> In-Reply-To: <20210121075149.1310-1-hailong.fan@mediatek.com> From: Nicolas Boichat Date: Thu, 21 Jan 2021 16:55:25 +0800 Message-ID: Subject: Re: [PATCH RESEND] pinctrl: mediatek: Fix trigger type setting follow for unexpected interrupt To: Hailong Fan Cc: Sean Wang , Linus Walleij , Matthias Brugger , "moderated list:ARM/Mediatek SoC support" , "open list:GPIO SUBSYSTEM" , linux-arm Mailing List , lkml , youlin.pei@mediatek.com, srv_heupstream , Chen-Tsung Hsieh , gtk_pangao@mediatek.com, Hanks Chen , Yong Wu Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 21, 2021 at 3:52 PM Hailong Fan wrote: > > When flipping the polarity will be generated interrupt under certain > circumstances, but GPIO external signal has not changed. > Then, mask the interrupt before polarity setting, and clear the > unexpected interrupt after trigger type setting completed. > > Signed-off-by: Hailong Fan > --- > Resend since some server reject. > --- > drivers/pinctrl/mediatek/mtk-eint.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c > index 22736f60c16c..3acda6bb401e 100644 > --- a/drivers/pinctrl/mediatek/mtk-eint.c > +++ b/drivers/pinctrl/mediatek/mtk-eint.c > @@ -157,6 +157,7 @@ static void mtk_eint_ack(struct irq_data *d) > static int mtk_eint_set_type(struct irq_data *d, unsigned int type) > { > struct mtk_eint *eint = irq_data_get_irq_chip_data(d); > + unsigned int unmask; bool? > u32 mask = BIT(d->hwirq & 0x1f); > void __iomem *reg; > > @@ -173,6 +174,13 @@ static int mtk_eint_set_type(struct irq_data *d, unsigned int type) > else > eint->dual_edge[d->hwirq] = 0; > > + if (!mtk_eint_get_mask(eint, d->hwirq)) { > + mtk_eint_mask(d); > + unmask = 1; > + } else { > + unmask = 0; > + } > + > if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) { > reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr); > writel(mask, reg); > @@ -189,8 +197,9 @@ static int mtk_eint_set_type(struct irq_data *d, unsigned int type) > writel(mask, reg); > } > > - if (eint->dual_edge[d->hwirq]) > - mtk_eint_flip_edge(eint, d->hwirq); Why are you dropping this? Aren't we at risk to miss the first edge after mtk_eint_set_type is called? > + mtk_eint_ack(d); > + if (unmask == 1) Just `if (unmask)` > + mtk_eint_unmask(d); > > return 0; > } > -- > 2.18.0