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Subject: Re: [RFC PATCH 7/7] irqchip/apple-aic: add SMP support to the Apple
 AIC driver.
From:   Mohamed Mediouni <mohamed.mediouni@caramail.com>
In-Reply-To: <CAL_JsqJq_wfLrJm8rwspkgz81Be2V9WTudRjMAXSrZD50ewFYA@mail.gmail.com>
Date:   Thu, 21 Jan 2021 17:43:03 +0100
Cc:     Arnd Bergmann <arnd@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Catalin Marinas <catalin.marinas@arm.com>,
        Hector Martin <marcan@marcan.st>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Marc Zyngier <maz@kernel.org>, Will Deacon <will@kernel.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        Stan Skowronek <stan@corellium.com>
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Message-Id: <FEDB12D6-2916-4430-A8DC-FBD9352F3730@caramail.com>
References: <20210120132717.395873-1-mohamed.mediouni@caramail.com>
 <20210120132717.395873-8-mohamed.mediouni@caramail.com>
 <CAK8P3a1qeVxTxZXpfMe70zpPCSBrTOz23ZTR=PHgw0PP9GUvbw@mail.gmail.com>
 <E77005CF-8B2A-4D17-9330-72ECFD7F3C93@caramail.com>
 <CAL_JsqJq_wfLrJm8rwspkgz81Be2V9WTudRjMAXSrZD50ewFYA@mail.gmail.com>
To:     Rob Herring <robh@kernel.org>
Precedence: bulk


> On 21 Jan 2021, at 17:40, Rob Herring <robh@kernel.org> wrote:
>=20
> On Thu, Jan 21, 2021 at 6:52 AM Mohamed Mediouni
> <mohamed.mediouni@caramail.com> wrote:
>>=20
>>=20
>>=20
>>> On 21 Jan 2021, at 13:44, Arnd Bergmann <arnd@kernel.org> wrote:
>>>=20
>>> On Wed, Jan 20, 2021 at 2:27 PM Mohamed Mediouni
>>> <mohamed.mediouni@caramail.com> wrote:
>>>=20
>>>> +#ifdef CONFIG_SMP
>>>> +static void apple_aic_ipi_send_mask(struct irq_data *d,
>>>> +                                   const struct cpumask *mask)
>>>=20
>>> Not sure we care about the #ifdef here, given that arch/arm64 does =
not
>>> allow building a kernel without CONFIG_SMP.
>>>=20
>>>> +       /*
>>>> +     * Ensure that stores to Normal memory are visible to the
>>>> +     * other CPUs before issuing the IPI.
>>>> +     */
>>>> +       wmb();
>>>> +
>>>> +       for_each_cpu (cpu, mask) {
>>>> +               smp_mb__before_atomic();
>>>> +               atomic_or(1u << irqnr, per_cpu_ptr(&aic_ipi_mask, =
cpu));
>>>> +               smp_mb__after_atomic();
>>>> +               lcpu =3D get_cpu();
>>>> +               if (aic.fast_ipi) {
>>>> +                       if ((lcpu >> 2) =3D=3D (cpu >> 2))
>>>> +                               write_sysreg(cpu & 3, =
SR_APPLE_IPI_LOCAL);
>>>> +                       else
>>>> +                               write_sysreg((cpu & 3) | ((cpu >> =
2) << 16),
>>>> +                                            SR_APPLE_IPI_REMOTE);
>>>> +               } else
>>>> +                       writel(lcpu =3D=3D cpu ? REG_IPI_FLAG_SELF =
:
>>>> +                                                  =
(REG_IPI_FLAG_OTHER << cpu),
>>>> +                              aic.base + REG_IPI_SET);
>>>> +               put_cpu();
>>>> +       }
>>>> +
>>>> +       /* Force the above writes to be executed */
>>>> +       if (aic.fast_ipi)
>>>> +               isb();
>>>> +}
>>>=20
>>> Since this just loops over all CPUs, I'd probably just turn it into
>>> an ipi_send_single() callback and have the caller do the
>>> loop for simplicity.
>>>=20
>>> I also have the feeling that splitting one hardware IPI into =
multiple
>>> logical interrupts, which are then all registered by the same irq
>>> handler adds a little more complexity than necessary.
>>>=20
>>> Changing this would of course require modifications to
>>> arch/arm64/kernel/smp.c, which is hardwired to use
>>> CONFIG_GENERIC_IRQ_IPI in smp_cross_call(), and allowing
>>> a different code path there may be worse than emulating an
>>> irqchip.
>>>=20
>>>> @@ -186,8 +325,11 @@ static int __init apple_aic_init(struct =
device_node *node,
>>>>      if (WARN(!aic.base, "unable to map aic registers\n"))
>>>>              return -EINVAL;
>>>>=20
>>>> +       aic.fast_ipi =3D of_property_read_bool(node, "fast-ipi");
>>>=20
>>> Where is this property documented, and what decides which one to =
use?
>> It=E2=80=99s getting documented in the next patch set.
>>=20
>> This property is there to enable support for older iPhone processors
>> later on, some of which do not have fast IPI support.
>>=20
>> On Apple M1, fast-ipi is always on.
>=20
> This should be implied by the compatible string which needs to be more
> specific and include the SoC name.
>=20
> Rob

Then we=E2=80=99ll eventually have two aic compatible strings, aic which =
is compatible
with Apple A7 onwards and aicv2 which is a superset with fast IPI =
(introduced=20
on the Apple A11, 3 years ago, with no further programmer-visible =
changes since=20
then).

Does that look right?

Thank you,=20