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From:   John Garry <john.garry@huawei.com>
Subject: Re: [PATCH v2 1/3] perf vendor events: Add cache refill and DCZVA
 events
To:     Shaokun Zhang <zhangshaokun@hisilicon.com>,
        Shunsuke Nakamura <nakamura.shun@jp.fujitsu.com>
CC:     <mathieu.poirier@linaro.org>, <linux-kernel@vger.kernel.org>,
        <leo.yan@linaro.org>, <will@kernel.org>,
        <linux-arm-kernel@lists.infradead.org>
References: <20210121105425.2695843-1-nakamura.shun@jp.fujitsu.com>
 <20210121105425.2695843-2-nakamura.shun@jp.fujitsu.com>
 <b00bf252-e31f-b0eb-d0aa-0a62bcaee22e@hisilicon.com>
Message-ID: <0be33a5d-98a1-d2e1-704e-83334063888d@huawei.com>
Date:   Thu, 21 Jan 2021 17:43:41 +0000
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On 21/01/2021 11:39, Shaokun Zhang wrote:
> Hi,
> 
> ?? 2021/1/21 18:54, Shunsuke Nakamura д??:
>> Adds L1 data cache refill prefetch, L2 data cache refill prefetch,
>> and DCZVA instruction events.
> 
> A silly question, Does Arm define these events? I checked Arm ARM
> document(DDI0487Fc) that these event numbers are reserved. Or maybe
> I miss something.

For events which are reserved (see k3-1), like 0x9f, prob should not be 
putting in this file, but rather the CPU JSON.

Cheers,
John

> 
>>
>> Signed-off-by: Shunsuke Nakamura <nakamura.shun@jp.fujitsu.com>
>> ---
>>   .../perf/pmu-events/arch/arm64/armv8-recommended.json  | 18 ++++++++++++++++++
>>   1 file changed, 18 insertions(+)
>>
>> diff --git a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
>> index d0a1986..ee0e67d 100644
>> --- a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
>> +++ b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
>> @@ -54,6 +54,12 @@
>>           "BriefDescription": "L1D cache invalidate"
>>       },
>>       {
>> +        "PublicDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch.",
>> +        "EventCode": "0x49",
>> +        "EventName": "L1D_CACHE_REFILL_PRF",
>> +        "BriefDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch."
>> +    },
>> +    {
>>           "PublicDescription": "Attributable Level 1 data TLB refill, read",
>>           "EventCode": "0x4C",
>>           "EventName": "L1D_TLB_REFILL_RD",
>> @@ -120,6 +126,12 @@
>>           "BriefDescription": "L2D cache invalidate"
>>       },
>>       {
>> +        "PublicDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch.",
>> +        "EventCode": "0x59",
>> +        "EventName": "L2D_CACHE_REFILL_PRF",
>> +        "BriefDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch."
>> +    },
>> +    {
>>           "PublicDescription": "Attributable Level 2 data or unified TLB refill, read",
>>           "EventCode": "0x5c",
>>           "EventName": "L2D_TLB_REFILL_RD",
>> @@ -408,6 +420,12 @@
>>           "BriefDescription": "Release consistency operation speculatively executed, Store-Release"
>>      },
>>      {
>> +         "PublicDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction.",
>> +         "EventCode": "0x9f",
>> +         "EventName": "DCZVA_SPEC",
>> +         "BriefDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction."
>> +   },
>> +   {
>>           "PublicDescription": "Attributable Level 3 data or unified cache access, read",
>>           "EventCode": "0xa0",
>>           "EventName": "L3D_CACHE_RD",
>>
> .
>