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From:   "nakamura.shun@fujitsu.com" <nakamura.shun@fujitsu.com>
To:     'John Garry' <john.garry@huawei.com>,
        Shaokun Zhang <zhangshaokun@hisilicon.com>
CC:     "mathieu.poirier@linaro.org" <mathieu.poirier@linaro.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "leo.yan@linaro.org" <leo.yan@linaro.org>,
        "will@kernel.org" <will@kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>
Subject: RE: [PATCH v2 1/3] perf vendor events: Add cache refill and DCZVA
 events
Thread-Topic: [PATCH v2 1/3] perf vendor events: Add cache refill and DCZVA
 events
Thread-Index: AQHW7+SfZlbnwAdjkk2qmbTsu5bGU6ox9FMAgABlzYCAANpbYA==
Date:   Fri, 22 Jan 2021 08:35:52 +0000
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Hi,  John, Shaokun

> > =1B$B:_=1B(B 2021/1/21 18:54, Shunsuke Nakamura =1B$B<LF;=1B(B:
> >> Adds L1 data cache refill prefetch, L2 data cache refill prefetch,
> >> and DCZVA instruction events.
> >
> > A silly question, Does Arm define these events? I checked Arm ARM
> > document(DDI0487Fc) that these event numbers are reserved. Or maybe I
> > miss something.
>=20
> For events which are reserved (see k3-1), like 0x9f, prob should not be p=
utting in
> this file, but rather the CPU JSON.

I missed the reservation area for ARM recommended events.
I will fix the patch as you pointed out.

Best Regards

> -----Original Message-----
> From: John Garry <john.garry@huawei.com>
> Sent: Friday, January 22, 2021 2:44 AM
> To: Shaokun Zhang <zhangshaokun@hisilicon.com>; Nakamura, Shunsuke/=1B$BC=
fB<=1B(B
> =1B$B=3DS2p=1B(B <nakamura.shun@fujitsu.com>
> Cc: mathieu.poirier@linaro.org; linux-kernel@vger.kernel.org;
> leo.yan@linaro.org; will@kernel.org; linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH v2 1/3] perf vendor events: Add cache refill and DCZV=
A
> events
>=20
> On 21/01/2021 11:39, Shaokun Zhang wrote:
> > Hi,
> >
> > =1B$B:_=1B(B 2021/1/21 18:54, Shunsuke Nakamura =1B$B<LF;=1B(B:
> >> Adds L1 data cache refill prefetch, L2 data cache refill prefetch,
> >> and DCZVA instruction events.
> >
> > A silly question, Does Arm define these events? I checked Arm ARM
> > document(DDI0487Fc) that these event numbers are reserved. Or maybe I
> > miss something.
>=20
> For events which are reserved (see k3-1), like 0x9f, prob should not be p=
utting in
> this file, but rather the CPU JSON.
>=20
> Cheers,
> John
>=20
> >
> >>
> >> Signed-off-by: Shunsuke Nakamura <nakamura.shun@jp.fujitsu.com>
> >> ---
> >>   .../perf/pmu-events/arch/arm64/armv8-recommended.json  | 18
> ++++++++++++++++++
> >>   1 file changed, 18 insertions(+)
> >>
> >> diff --git a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
> >> b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
> >> index d0a1986..ee0e67d 100644
> >> --- a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
> >> +++ b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
> >> @@ -54,6 +54,12 @@
> >>           "BriefDescription": "L1D cache invalidate"
> >>       },
> >>       {
> >> +        "PublicDescription": "This event counts L1D_CACHE_REFILL
> caused by software or hardware prefetch.",
> >> +        "EventCode": "0x49",
> >> +        "EventName": "L1D_CACHE_REFILL_PRF",
> >> +        "BriefDescription": "This event counts L1D_CACHE_REFILL cause=
d
> by software or hardware prefetch."
> >> +    },
> >> +    {
> >>           "PublicDescription": "Attributable Level 1 data TLB refill, =
read",
> >>           "EventCode": "0x4C",
> >>           "EventName": "L1D_TLB_REFILL_RD", @@ -120,6 +126,12 @@
> >>           "BriefDescription": "L2D cache invalidate"
> >>       },
> >>       {
> >> +        "PublicDescription": "This event counts L2D_CACHE_REFILL
> caused by software or hardware prefetch.",
> >> +        "EventCode": "0x59",
> >> +        "EventName": "L2D_CACHE_REFILL_PRF",
> >> +        "BriefDescription": "This event counts L2D_CACHE_REFILL cause=
d
> by software or hardware prefetch."
> >> +    },
> >> +    {
> >>           "PublicDescription": "Attributable Level 2 data or unified T=
LB refill,
> read",
> >>           "EventCode": "0x5c",
> >>           "EventName": "L2D_TLB_REFILL_RD", @@ -408,6 +420,12 @@
> >>           "BriefDescription": "Release consistency operation speculati=
vely
> executed, Store-Release"
> >>      },
> >>      {
> >> +         "PublicDescription": "This event counts architecturally exec=
uted
> zero blocking operations due to the 'DC ZVA' instruction.",
> >> +         "EventCode": "0x9f",
> >> +         "EventName": "DCZVA_SPEC",
> >> +         "BriefDescription": "This event counts architecturally execu=
ted
> zero blocking operations due to the 'DC ZVA' instruction."
> >> +   },
> >> +   {
> >>           "PublicDescription": "Attributable Level 3 data or unified c=
ache
> access, read",
> >>           "EventCode": "0xa0",
> >>           "EventName": "L3D_CACHE_RD",
> >>
> > .
> >