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[23.128.96.18]) by mx.google.com with ESMTP id c5si5078858ejz.259.2021.01.24.06.13.09; Sun, 24 Jan 2021 06:13:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=TBkJ6nom; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726202AbhAXOMQ (ORCPT + 99 others); Sun, 24 Jan 2021 09:12:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725794AbhAXOMG (ORCPT ); Sun, 24 Jan 2021 09:12:06 -0500 Received: from mail-io1-xd33.google.com (mail-io1-xd33.google.com [IPv6:2607:f8b0:4864:20::d33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43E84C061573; Sun, 24 Jan 2021 06:11:26 -0800 (PST) Received: by mail-io1-xd33.google.com with SMTP id x21so21172047iog.10; Sun, 24 Jan 2021 06:11:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=0Ao/yarVyR+Aon04nX87tyRiOiK8ZlEZS4G8Yy79d54=; b=TBkJ6nomCk8/2cv7rEzXhkIJHSRYlN/B20umDI5FBypSXY4LiVPvMYkZ78nB0graug gySN6qtT5tUkrEvc6+TXZP+uf8C6cziH+LvxTvGjYKvAJ5T/3X7OkFwMVs4dxtFZ/z5K OgXcxITHmq15P9yHxa8MBf8MAT8zpKYkt+Aw//x97N6VRwmDjJElxZ+jYmCinRwCsEup chv3TFU2MILu2qa3ld8TSXvqHYeZ75983Br0qd0yD64NSLXkt0ShGnq0/dx9VFfGxEJR zgAVgvSAeNvbJrbbZZ0lZrsALbx10cfXv/YqMvWBQbX4V5+h5oGxhe5G2jiv+eJGRzN8 j0lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=0Ao/yarVyR+Aon04nX87tyRiOiK8ZlEZS4G8Yy79d54=; b=BtLavFlaMx5D5zwNCoaCsOuDPLtI9FUVSvqnbv66LNGGzAW/ELC/lS6wI1uZBsZV5e L+GH1cqUOPgIAO7Hg3bHc0utMgC49X7KY1zFgpM6q1k/W4GAlDdB6yHtGp2bpOI+dWUp gSDvq5oq99RYMf8qwGVIfXp2f9HtHOKL6p/cu4fAnuAGEUMu+5AxVN2+G4NPvpICi+lB YR/wf3AEcfCoyvHMSn+sNtoKfJAoyvI+CYe9yKIj8IMcWAtfI67VAHm5VJ7prqUlW7eN HNtzMfbot6T1+HRiiw4i8xrm1pRy/IuFvTRKYWcpvjHnsAT6GacLK8E6yExYmLyE8WjU m0iw== X-Gm-Message-State: AOAM5311b8ZUlaYzfzIVMCP+rVQk2Fv90GiA0HugCdTohbyWkruV5YlG x2FFvgHfgj5cTi7yJ0oYcF3NRnQbtXKPqR6GpCA= X-Received: by 2002:a6b:8d0f:: with SMTP id p15mr4436364iod.56.1611497485689; Sun, 24 Jan 2021 06:11:25 -0800 (PST) MIME-Version: 1.0 References: <20200907131613.12703-1-joro@8bytes.org> <20200907131613.12703-46-joro@8bytes.org> In-Reply-To: <20200907131613.12703-46-joro@8bytes.org> From: Lai Jiangshan Date: Sun, 24 Jan 2021 22:11:14 +0800 Message-ID: Subject: Re: [PATCH v7 45/72] x86/entry/64: Add entry code for #VC handler To: Joerg Roedel Cc: X86 ML , Joerg Roedel , "H. Peter Anvin" , Andy Lutomirski , Dave Hansen , Peter Zijlstra , Jiri Slaby , Dan Williams , Tom Lendacky , Juergen Gross , Kees Cook , David Rientjes , Cfir Cohen , Erdem Aktas , Masami Hiramatsu , Mike Stunes , Sean Christopherson , Martin Radev , LKML , kvm@vger.kernel.org, virtualization@lists.linux-foundation.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > + > + /* > + * No need to switch back to the IST stack. The current stack is either > + * identical to the stack in the IRET frame or the VC fall-back stack, > + * so it is definitly mapped even with PTI enabled. > + */ > + jmp paranoid_exit > + > Hello I know we don't enable PTI on AMD, but the above comment doesn't align to the next code. We assume PTI is enabled as the comments said "even with PTI enabled". When #VC happens after entry_SYSCALL_64 but before it switches to the kernel CR3. vc_switch_off_ist() will switch the stack to the kernel stack and paranoid_exit can't work when it switches to user CR3 on the kernel stack. The comment above lost information that the current stack is possible to be the kernel stack which is mapped not user CR3. Maybe I missed something. Thanks Lai > +#ifdef CONFIG_AMD_MEM_ENCRYPT > +asmlinkage __visible noinstr struct pt_regs *vc_switch_off_ist(struct pt_regs *regs) > +{ > + unsigned long sp, *stack; > + struct stack_info info; > + struct pt_regs *regs_ret; > + > + /* > + * In the SYSCALL entry path the RSP value comes from user-space - don't > + * trust it and switch to the current kernel stack > + */ > + if (regs->ip >= (unsigned long)entry_SYSCALL_64 && > + regs->ip < (unsigned long)entry_SYSCALL_64_safe_stack) { > + sp = this_cpu_read(cpu_current_top_of_stack); > + goto sync; > + }