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[23.128.96.18]) by mx.google.com with ESMTP id gf11si5568202ejb.179.2021.01.24.19.25.46; Sun, 24 Jan 2021 19:26:11 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=DxgVfbgS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727014AbhAYDZJ (ORCPT + 99 others); Sun, 24 Jan 2021 22:25:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726863AbhAYDZI (ORCPT ); Sun, 24 Jan 2021 22:25:08 -0500 Received: from mail-ua1-x936.google.com (mail-ua1-x936.google.com [IPv6:2607:f8b0:4864:20::936]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6193C061574 for ; Sun, 24 Jan 2021 19:24:27 -0800 (PST) Received: by mail-ua1-x936.google.com with SMTP id u27so3973854uaa.13 for ; Sun, 24 Jan 2021 19:24:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=mCmh2kWpn9Xf7nqnBfNwjaSrOMJ8Dlsin1zC2EYEHJM=; b=DxgVfbgSgEU3qgjORZIqffrN0lR2zv6uJlzsMyt1HdJ74Zta1SnL83jfWhNjn/ka8V TeU18fLLS7MzAQMqTJQkUKs9gNo1UIWDxHy31rUO1XBhmxpi9c8NUkO3LqH124Y291qe /pAoAw1tjynLxxN3eNPD/F8GUhnNuYTmh8ZKQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=mCmh2kWpn9Xf7nqnBfNwjaSrOMJ8Dlsin1zC2EYEHJM=; b=bR9oG3oja/uowOjIA9048KfZzfCaxlBudf1pfZ+WmyPnpu4IJGmgzQ+GmTk4hQ1bw6 PW5yIwjvAgxAOGajYz45WOmubBdTOSCDANWLY0ea4wSzsnFIotMTl0Xwbxq8JARxqIYN 60yLKSA9KwsdM1FuTFQaA9JaVQciKM+zXzmcyskfRixWLmY9h+dchrqavQ20MXKVhhvO E+/1araLk0tHHHuhRmuiQ1r/WBItYfSVjN8nj1w3OETNDOHRHQWBAI7xHS7XDjeE20+W ww8foZstJNCXvgBKdFHw3ZsGo3Kj/x68oKuOVEvvOfhjzWHflD+L84bWEqpwXiea3UDs kEaw== X-Gm-Message-State: AOAM533E8AHqnO5GrZ2yrYufh/9amV8DJP0LijLhaB8p7J94A6Zojiqr MTRkY/jdVQwuBpfVV2a3tPT8j33jK/icDZCKXBow6w== X-Received: by 2002:ab0:3043:: with SMTP id x3mr105842ual.88.1611545066853; Sun, 24 Jan 2021 19:24:26 -0800 (PST) MIME-Version: 1.0 References: <20210125031513.1741-1-hailong.fan@mediatek.com> In-Reply-To: <20210125031513.1741-1-hailong.fan@mediatek.com> From: Nicolas Boichat Date: Mon, 25 Jan 2021 11:24:16 +0800 Message-ID: Subject: Re: [PATCH] pinctrl: mediatek: Fix trigger type setting follow for unexpected interrupt To: Hailong Fan Cc: Sean Wang , Linus Walleij , Matthias Brugger , "moderated list:ARM/Mediatek SoC support" , "open list:GPIO SUBSYSTEM" , linux-arm Mailing List , lkml , youlin.pei@mediatek.com, srv_heupstream , Chen-Tsung Hsieh , gtk_pangao@mediatek.com, Hanks Chen , Yong Wu Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jan 25, 2021 at 11:15 AM Hailong Fan wrote: > > When flipping the polarity will be generated interrupt under certain > circumstances, but GPIO external signal has not changed. > Then, mask the interrupt before polarity setting, and clear the > unexpected interrupt after trigger type setting completed. I'd add a short note about why you remove mtk_eint_flip_edge, that is, because mtk_eint_unmask already calls it. > > Signed-off-by: Hailong Fan > --- > [V2] > --- > drivers/pinctrl/mediatek/mtk-eint.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c > index 22736f60c16c..0042f32c7e7e 100644 > --- a/drivers/pinctrl/mediatek/mtk-eint.c > +++ b/drivers/pinctrl/mediatek/mtk-eint.c > @@ -157,6 +157,7 @@ static void mtk_eint_ack(struct irq_data *d) > static int mtk_eint_set_type(struct irq_data *d, unsigned int type) > { > struct mtk_eint *eint = irq_data_get_irq_chip_data(d); > + bool unmasked; Well, this is true if the interrupt has been masked (or, equivalently, if we need to unmask it later). So I think either "masked" or "unmask" are better as variable names. > u32 mask = BIT(d->hwirq & 0x1f); > void __iomem *reg; > > @@ -173,6 +174,13 @@ static int mtk_eint_set_type(struct irq_data *d, unsigned int type) > else > eint->dual_edge[d->hwirq] = 0; > > + if (!mtk_eint_get_mask(eint, d->hwirq)) { > + mtk_eint_mask(d); > + unmasked = true; > + } else { > + unmasked = false; > + } > + > if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) { > reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr); > writel(mask, reg); > @@ -189,8 +197,9 @@ static int mtk_eint_set_type(struct irq_data *d, unsigned int type) > writel(mask, reg); > } > > - if (eint->dual_edge[d->hwirq]) > - mtk_eint_flip_edge(eint, d->hwirq); > + mtk_eint_ack(d); > + if (unmasked) > + mtk_eint_unmask(d); > > return 0; > } > -- > 2.18.0