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Mon, 25 Jan 2021 04:36:33 +0000 Date: Mon, 25 Jan 2021 12:36:23 +0800 From: Huang Rui To: Colin King Cc: "Deucher, Alexander" , "Koenig, Christian" , David Airlie , Daniel Vetter , "Liu, Aaron" , "amd-gfx@lists.freedesktop.org" , "dri-devel@lists.freedesktop.org" , "kernel-janitors@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH][next] drm/amdgpu: Fix masking binary not operator on two mask operations Message-ID: <20210125043623.GD610615@hr-amd> References: <20210122150022.209454-1-colin.king@canonical.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210122150022.209454-1-colin.king@canonical.com> X-Originating-IP: [180.167.199.189] X-ClientProxiedBy: HK2PR04CA0082.apcprd04.prod.outlook.com (2603:1096:202:15::26) To MWHPR12MB1248.namprd12.prod.outlook.com (2603:10b6:300:12::21) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from hr-amd (180.167.199.189) by HK2PR04CA0082.apcprd04.prod.outlook.com (2603:1096:202:15::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3784.12 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?odoEf2JrF2kuloeOUzfCXFEWv44K9tyHk/JS8VJjXFsTh13lc2evvJVm+NJn?= =?us-ascii?Q?wu5dpSOIf/4iFldQUvGYHIcxc79/s21vCz31POdFgVcbg9/tjLd+Gg7jQiDT?= =?us-ascii?Q?cv9O8mp2bQG0R1pRW5zXMilwAEpwJOJFFbrxAekqaq5tBRHQNGAEDALIhFQb?= =?us-ascii?Q?xwpFsSJP5AmTbgi96o640RwVCV+Aw6EVfewA0GMtyPAis2TdA7hAC0yKncCb?= =?us-ascii?Q?/4My/8OFTtMmCjmIWsp6+SlCUYLojOXFCYit+5+wFIGPhySYD9MmB9x8WyZh?= =?us-ascii?Q?cn12f4Jg/M+hYk7qPDK7qVIU1fd3jVwdIJI6NQjmI58FQVwJ4IpQrl04WQxe?= =?us-ascii?Q?Lji7J1bsueV1G4Tiet7eSFZ0CS72wk1+lJXO7UubGleRwq2DGkz1+HrV2C5w?= =?us-ascii?Q?jZec4H/mrppt0yIgsEp/sgTQQwZLKvSOZFQ9CtQn4qC2ZeOboo2X1SYSV7O8?= =?us-ascii?Q?TJp9PxJdAKTwiTQzEFc9a+VRsxXB8DrrGqVpTKkbD5J9B5mAnvMtbsrDKcC0?= =?us-ascii?Q?iKQVERpcDmUN7g/gQISQJ/yCgYt70ovllpBGIJwJ7FaXJ6W6Z4mi4ISn/lS7?= =?us-ascii?Q?lCjVi+Ar6jRbNYlO9/q/zab6uXCDDpxsr7yIpQAVGgrdLZIKuhXjk+fzErVf?= =?us-ascii?Q?+P43tkyrg5c7BoGBrQCHCsXisI34Ay+FNFHLN96TETMehQuOgcfI8tM6CDag?= =?us-ascii?Q?Z0IZhyQkvfens6hsOzR6PEQfiNDvJyGpOzJRBkFebiF68cyTnCKgRswczXxq?= =?us-ascii?Q?4Op7G2KgxggAsFqAz4+3Mpv2plJ1bob4ioKynJs+32c7fpVVEBxZ/vBXmLcv?= =?us-ascii?Q?eN4xunSy/BPUa0kXd4N0PuW86SrUak/ElAgLAvuNJ9z91OLTOp9pg5D48tmc?= =?us-ascii?Q?JAA1CjaUiGH0EW27gF5zuRSpJdHWQV3hKyOIj1hfuI6yCmJ7hiE1Mviz2qy1?= =?us-ascii?Q?K1LxmC7y0nc+VnWiA0/U/0EX9cyk6asSRgQpgwY7g/T5fj6AVfhY/+MJM6bB?= =?us-ascii?Q?rwzkkynpMfTYqiKIKEX4xQ77cl/0p2OnJspVHvlDtSEuTJNmcYywJ2g2eWk2?= =?us-ascii?Q?49DrTHOWg9WgAYFmp5Ln+s0QWtSXeg=3D=3D?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: a7368bbc-9862-4101-ab46-08d8c0eaca9e X-MS-Exchange-CrossTenant-AuthSource: MWHPR12MB1248.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jan 2021 04:36:33.2129 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: lKQi7Z2PdrU354VFuG7Yqd/5mvJFuOsvRcL3p2bE1TCqnYhBKCnGCO+sSgqAaEvYf+T8kxuU0elkdjh6YuRhKA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR12MB2459 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jan 22, 2021 at 11:00:22PM +0800, Colin King wrote: > From: Colin Ian King > > Currently the ! operator is incorrectly being used to flip bits on > mask values. Fix this by using the bit-wise ~ operator instead. > > Addresses-Coverity: ("Logical vs. bitwise operator") > Fixes: 3c9a7b7d6e75 ("drm/amdgpu: update mmhub mgcg&ls for mmhub_v2_3") > Signed-off-by: Colin Ian King Thanks. Reviewed-by: Huang Rui > --- > drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c > index 1961745e89c7..ab9be5ad5a5f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c > @@ -531,12 +531,12 @@ mmhub_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev, > > if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) { > data &= ~MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK; > - data1 &= !(DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK | > + data1 &= ~(DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK | > DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK | > DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK | > DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK | > DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK); > - data2 &= !(DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK | > + data2 &= ~(DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK | > DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK | > DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK | > DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK | > -- > 2.29.2 >