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Date:   Mon, 25 Jan 2021 20:19:57 +0100
From:   Krzysztof Kozlowski <krzk@kernel.org>
To:     Adam Ford <aford173@gmail.com>
Cc:     linux-arm-kernel@lists.infradead.org, aford@beaconembedded.com,
        Rob Herring <robh+dt@kernel.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] arm64: dts: imx8mn-beacon-som: Enable QSPI on SOM
Message-ID: <20210125191957.nrc2saxqebt6tjic@kozik-lap>
References: <20210119134258.774480-1-aford173@gmail.com>
 <20210119134258.774480-2-aford173@gmail.com>
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On Tue, Jan 19, 2021 at 07:42:58AM -0600, Adam Ford wrote:
> There is a QSPI chip connected to the FlexSPI bus.  Enable it.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
> index 2120e6485393..9f575184d899 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi
> @@ -7,6 +7,7 @@ / {
>  	aliases {
>  		rtc0 = &rtc;
>  		rtc1 = &snvs_rtc;
> +		spi0 = &flexspi;
>  	};
>  
>  	usdhc1_pwrseq: usdhc1_pwrseq {
> @@ -89,6 +90,22 @@ ethphy0: ethernet-phy@0 {
>  	};
>  };
>  
> +&flexspi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_flexspi>;
> +	status = "okay";
> +
> +	flash@0 {
> +		reg = <0>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "jedec,spi-nor";
> +		spi-max-frequency = <80000000>;
> +		spi-tx-bus-width = <4>;
> +		spi-rx-bus-width = <4>;
> +	};
> +};
> +
>  &i2c1 {
>  	clock-frequency = <400000>;
>  	pinctrl-names = "default";
> @@ -318,6 +335,18 @@ MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
>  		>;
>  	};
>  
> +	pinctrl_flexspi: flexspigrp {
> +		fsl,pins = <
> +			MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
> +			MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
> +			MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
> +			MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
> +			MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
> +			MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
> +		>;
> +	};
> +
> +

Double line break. Beside that:

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof