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Subject: Re: [PATCH] perf/intel: Remove Perfmon-v4 counter_freezing support
To:     "Xu, Like" <like.xu@intel.com>,
        Stephane Eranian <eranian@google.com>,
        Peter Zijlstra <peterz@infradead.org>
Cc:     Like Xu <like.xu@linux.intel.com>, kvm@vger.kernel.org,
        Sean Christopherson <sean.j.christopherson@intel.com>,
        Vitaly Kuznetsov <vkuznets@redhat.com>,
        Wanpeng Li <wanpengli@tencent.com>,
        Jim Mattson <jmattson@google.com>,
        Joerg Roedel <joro@8bytes.org>,
        Kan Liang <kan.liang@linux.intel.com>, luwei.kang@intel.com,
        Thomas Gleixner <tglx@linutronix.de>,
        "Wang, Wei W" <wei.w.wang@intel.com>,
        Tony Luck <tony.luck@intel.com>,
        Mark Gross <mgross@linux.intel.com>,
        Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>,
        LKML <linux-kernel@vger.kernel.org>
References: <20201109021254.79755-1-like.xu@linux.intel.com>
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 <20201110153721.GQ2651@hirez.programming.kicks-ass.net>
 <CABPqkBS+-g0qbsruAMfOJf-Zfac8nz9v2LCWfrrvVd+ptoLxZg@mail.gmail.com>
 <2ce24056-0711-26b3-a62c-3bedc88d7aa7@intel.com>
From:   Paolo Bonzini <pbonzini@redhat.com>
Message-ID: <9a85e154-d552-3478-6e99-3f693b3da7ed@redhat.com>
Date:   Tue, 26 Jan 2021 10:51:39 +0100
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On 11/11/20 03:42, Xu, Like wrote:
> Hi Peter,
> 
> On 2020/11/11 4:52, Stephane Eranian wrote:
>> On Tue, Nov 10, 2020 at 7:37 AM Peter Zijlstra<peterz@infradead.org>  
>> wrote:
>>> On Tue, Nov 10, 2020 at 04:12:57PM +0100, Peter Zijlstra wrote:
>>>> On Mon, Nov 09, 2020 at 10:12:37AM +0800, Like Xu wrote:
>>>>> The Precise Event Based Sampling(PEBS) supported on Intel Ice Lake 
>>>>> server
>>>>> platforms can provide an architectural state of the instruction 
>>>>> executed
>>>>> after the instruction that caused the event. This patch set enables 
>>>>> the
>>>>> the PEBS via DS feature for KVM (also non) Linux guest on the Ice 
>>>>> Lake.
>>>>> The Linux guest can use PEBS feature like native:
>>>>>
>>>>>    # perf record -e instructions:ppp ./br_instr a
>>>>>    # perf record -c 100000 -e instructions:pp ./br_instr a
>>>>>
>>>>> If the counter_freezing is not enabled on the host, the guest PEBS 
>>>>> will
>>>>> be disabled on purpose when host is using PEBS facility. By default,
>>>>> KVM disables the co-existence of guest PEBS and host PEBS.
> Thanks Stephane for clarifying the use cases for Freeze-on-[PMI|Overflow].
> 
> Please let me express it more clearly.
> 
> The goal of the whole patch set is to enable guest PEBS, regardless of
> whether the counter_freezing is frozen or not. By default, it will not
> support both the guest and the host to use PEBS at the same time.
> 
> Please continue reviewing the patch set, especially for the slow path
> we proposed this time and related host perf changes:
> 
> - add intel_pmu_handle_guest_pebs() to __intel_pmu_pebs_event();
> - add switch MSRs (PEBS_ENABLE, DS_AREA, DATA_CFG) to 
> intel_guest_get_msrs();
> - the construction of incoming parameters for 
> perf_event_create_kernel_counter();
> 
> I believe if you understand the general idea, the comments will be very 
> valuable.

What is the state of this work?  I was expecting a new version that 
doesn't use counter_freezing.  However, I see that counter_freezing is 
still in there, so this patch from Peter has never been applied.

Paolo