Received: by 2002:a05:6a10:8c0a:0:0:0:0 with SMTP id go10csp3803328pxb; Tue, 26 Jan 2021 05:20:42 -0800 (PST) X-Google-Smtp-Source: ABdhPJxe/+Q46dD2B7TWul9f7cKuFvcD1GEdxZF8dzdFZWbg6beOn351cnh9hR1Mw4i2BNB12Grm X-Received: by 2002:a17:906:76d6:: with SMTP id q22mr3348491ejn.221.1611667242478; Tue, 26 Jan 2021 05:20:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611667242; cv=none; d=google.com; s=arc-20160816; b=PkYcjUZVy3Gi06TawSnUjxR/Fazf/+veY/9iQV+1u/f4JYRE0oi0IMcpJUBkXhbwYF G2VumWNaCOdWUwsIT691JB/MAe1FndDXgIzHQUriDu09FUP+lTR+Oe+y0rqwNDT81Fhk PnCx3Sg4gXAr/JuIp9+uufrsVAQX3Cd2ghTy9AqowLk1WNwpPjbLbjY5Kez5+GPRUdzu /qFFCjpCeK3wbQPwUke25XLh/BUY1p/xpAKiPGzvM1UPOLTnR+jVS/OPM3zLpO/FTRHw Zi4cV3fAjN2JSqUmu/7clvnRxfq8k5KeWXOd+DLz5nG1ZJBCws3kVSwCjP5sbPBARTo1 mnXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=NNHi0cbW8u4fPu9P4tXL4874OZEuY7Aho2CQDiwYIO0=; b=QsHz/DEgBcoEMti9+6EGWStdiexeCljGOt9FMvV30SwEbj0qRWcuKFlwYr3MJhedfg IPtl2nU1pynLJ15OMJKbjC6uWnZkWesO6LlTKHaSMqQ5wl3G9JJ14Aj8FrYxPtkBhl1Z vDk6EoIXqX70llaPWElpISvuu7yBTV8rP+adv7N9KzEYFDSP/AwckLmc3Bf6JWRSagrB /PgS6xop5taQqUwogrZS7C10h5/6EeVGb51dKf2ysdG5iap/a3iz7/dbc90+cry2fF8u /OuhzYOgsNtgFlYgn2f/2zIgbtbQ7fIW2Z+P8RWmR87fhj8dakvUJfV1JvjbjI273VoL 2DEg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ji7si6861188ejc.617.2021.01.26.05.20.16; Tue, 26 Jan 2021 05:20:42 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404408AbhAZNTN (ORCPT + 99 others); Tue, 26 Jan 2021 08:19:13 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:11504 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391781AbhAZMp6 (ORCPT ); Tue, 26 Jan 2021 07:45:58 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4DQ5yR0MSnzjDYt; Tue, 26 Jan 2021 20:43:59 +0800 (CST) Received: from DESKTOP-5IS4806.china.huawei.com (10.174.184.42) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.498.0; Tue, 26 Jan 2021 20:45:02 +0800 From: Keqian Zhu To: , , , , Marc Zyngier , Will Deacon , Catalin Marinas CC: Alex Williamson , Kirti Wankhede , Cornelia Huck , Mark Rutland , James Morse , Robin Murphy , Suzuki K Poulose , , , , , Subject: [RFC PATCH 1/7] arm64: cpufeature: Add API to report system support of HWDBM Date: Tue, 26 Jan 2021 20:44:38 +0800 Message-ID: <20210126124444.27136-2-zhukeqian1@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20210126124444.27136-1-zhukeqian1@huawei.com> References: <20210126124444.27136-1-zhukeqian1@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.174.184.42] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Though we already has a cpu capability named ARM64_HW_DBM, it's a LOCAL_CPU cap and conditionally compiled by CONFIG_ARM64_HW_AFDBM. This reports the system wide support of HW_DBM. Signed-off-by: Keqian Zhu --- arch/arm64/include/asm/cpufeature.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 9a555809b89c..dfded86c7684 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -664,6 +664,18 @@ static inline bool system_supports_mixed_endian(void) return val == 0x1; } +static inline bool system_supports_hw_dbm(void) +{ + u64 mmfr1; + u32 val; + + mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); + val = cpuid_feature_extract_unsigned_field(mmfr1, + ID_AA64MMFR1_HADBS_SHIFT); + + return val == 0x2; +} + static __always_inline bool system_supports_fpsimd(void) { return !cpus_have_const_cap(ARM64_HAS_NO_FPSIMD); -- 2.19.1