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Date:   Tue, 26 Jan 2021 18:25:33 -0800
From:   Jakub Kicinski <kuba@kernel.org>
To:     Laurent Badel <laurentbadel@eaton.com>
Cc:     Fugang Duan <fugang.duan@nxp.com>,
        "David S . Miller" <davem@davemloft.net>,
        Liam Girdwood <lgirdwood@gmail.com>,
        Mark Brown <broonie@kernel.org>, <netdev@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 net 1/1] net: fec: Fix temporary RMII clock reset on
 link up
Message-ID: <20210126182533.17ab52a9@kicinski-fedora-pc1c0hjn.dhcp.thefacebook.com>
In-Reply-To: <20210125100745.5090-2-laurentbadel@eaton.com>
References: <20210125100745.5090-1-laurentbadel@eaton.com>
        <20210125100745.5090-2-laurentbadel@eaton.com>
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On Mon, 25 Jan 2021 11:07:45 +0100 Laurent Badel wrote:
> =EF=BB=BFfec_restart() does a hard reset of the MAC module when the link =
status
> changes to up. This temporarily resets the R_CNTRL register which controls
> the MII mode of the ENET_OUT clock. In the case of RMII, the clock
> frequency momentarily drops from 50MHz to 25MHz until the register is
> reconfigured. Some link partners do not tolerate this glitch and
> invalidate the link causing failure to establish a stable link when using
> PHY polling mode. Since as per IEEE802.11 the criteria for link validity

I think you meant 802.3, fixed that up and applied, thanks!

> are PHY-specific, what the partner should tolerate cannot be assumed, so
> avoid resetting the MII clock by using software reset instead of hardware
> reset when the link is up. This is generally relevant only if the SoC
> provides the clock to an external PHY and the PHY is configured for RMII.