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From:   "Shradha Todi" <shradha.t@samsung.com>
To:     <linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>
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        <hari.tv@samsung.com>
In-Reply-To: <1609930210-19227-1-git-send-email-shradha.t@samsung.com>
Subject: RE: [PATCH v2] PCI: dwc: Add upper limit address for outbound iATU
Date:   Wed, 27 Jan 2021 14:46:51 +0530
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References: <CGME20210106105019epcas5p377bdbff5cd9e14e5107ccbf2b87b5754@epcas5p3.samsung.com>
        <1609930210-19227-1-git-send-email-shradha.t@samsung.com>
Precedence: bulk

Hi,
Gentle Ping..

Thanks

> -----Original Message-----
> From: Shradha Todi <shradha.t=40samsung.com>
> Sent: Wednesday, January 6, 2021 4:20 PM
> Subject: =5BPATCH v2=5D PCI: dwc: Add upper limit address for outbound iA=
TU
>=20
> The size parameter is unsigned long type which can accept size > 4GB. In =
that
> case, the upper limit address must be programmed. Add support to program =
the
> upper limit address and set INCREASE_REGION_SIZE in case size > 4GB.
>=20
> Signed-off-by: Shradha Todi <shradha.t=40samsung.com>
> ---
> v1: https://lkml.org/lkml/2020/12/20/187
> v2:
>    Addressed Rob's review comment and added PCI version check condition t=
o
>    avoid writing to reserved registers.
>=20
>  drivers/pci/controller/dwc/pcie-designware.c =7C 9 +++++++--
> drivers/pci/controller/dwc/pcie-designware.h =7C 1 +
>  2 files changed, 8 insertions(+), 2 deletions(-)
>=20
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c
> b/drivers/pci/controller/dwc/pcie-designware.c
> index 74590c7..1d62ca9 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> =40=40 -290,12 +290,17 =40=40 static void __dw_pcie_prog_outbound_atu(str=
uct
> dw_pcie *pci, u8 func_no,
>  			   upper_32_bits(cpu_addr));
>  	dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
>  			   lower_32_bits(cpu_addr + size - 1));
> +	if (pci->version >=3D 0x460A)
> +		dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_LIMIT,
> +				   upper_32_bits(cpu_addr + size - 1));
>  	dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
>  			   lower_32_bits(pci_addr));
>  	dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
>  			   upper_32_bits(pci_addr));
> -	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type =7C
> -			   PCIE_ATU_FUNC_NUM(func_no));
> +	val =3D type =7C PCIE_ATU_FUNC_NUM(func_no);
> +	val =3D ((upper_32_bits(size - 1)) && (pci->version >=3D 0x460A)) ?
> +		val =7C PCIE_ATU_INCREASE_REGION_SIZE : val;
> +	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val);
>  	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
>=20
>  	/*
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h
> b/drivers/pci/controller/dwc/pcie-designware.h
> index 8b905a2..7da79eb 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> =40=40 -102,6 +102,7 =40=40
>  =23define PCIE_ATU_DEV(x)			FIELD_PREP(GENMASK(23, 19),
> x)
>  =23define PCIE_ATU_FUNC(x)		FIELD_PREP(GENMASK(18, 16), x)
>  =23define PCIE_ATU_UPPER_TARGET		0x91C
> +=23define PCIE_ATU_UPPER_LIMIT		0x924
>=20
>  =23define PCIE_MISC_CONTROL_1_OFF		0x8BC
>  =23define PCIE_DBI_RO_WR_EN		BIT(0)
> --
> 2.7.4