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X-OriginatorOrg: nokia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2021 20:36:34.0685 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8a9629a6-88ea-4acf-29e2-08d8c3033c9b X-MS-Exchange-CrossTenant-Id: 5d471751-9675-428d-917b-70f44f9630b0 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5d471751-9675-428d-917b-70f44f9630b0;Ip=[131.228.2.8];Helo=[fihe3nok0734.emea.nsn-net.net] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT005.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0701MB2762 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alexander Sverdlin On Octeon mmiowb() is SYNCW, which is already contained in smp_store_release(). Removing superfluous barrier brings around 10% performance on uncontended tight spinlock loops. Signed-off-by: Alexander Sverdlin --- arch/mips/include/asm/spinlock.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h index 0a707f3..fbe97b4 100644 --- a/arch/mips/include/asm/spinlock.h +++ b/arch/mips/include/asm/spinlock.h @@ -21,8 +21,10 @@ */ static inline void queued_spin_unlock(struct qspinlock *lock) { +#ifndef CONFIG_CPU_CAVIUM_OCTEON /* This could be optimised with ARCH_HAS_MMIOWB */ mmiowb(); +#endif smp_store_release(&lock->locked, 0); #ifdef CONFIG_CPU_CAVIUM_OCTEON nudge_writes(); -- 2.10.2