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Subject: Re: [PATCH 2/4] perf vendor events arm64: Add common and uarch event
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From:   John Garry <john.garry@huawei.com>
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Date:   Thu, 28 Jan 2021 08:41:57 +0000
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On 28/01/2021 05:30, nakamura.shun@fujitsu.com wrote:
> Hi ,john
> 
> I would like to make a comment because there is excess or deficiency in comma.
> There are no differences in pmu-events.c.
> 
>> +    {
>> +        "PublicDescription": "Attributable Bus access",
>> +        "EventCode": "0x19",
>> +        "EventName": "BUS_ACCESS",
>> +        "BriefDescription": "Attributable Bus access",
>> +    },
> Comma is not required at the end of BriefDescription.
> 
>> +    {
>> +        "PublicDescription": "Bus cycle"
>> +        "EventCode": "0x1D",
>> +        "EventName": "BUS_CYCLES",
>> +        "BriefDescription": "Bus cycle"
>> +    },
> Missing comma at end of PublicDescription.
> 
>> +    {
>> +        "PublicDescription": "Attributable Last level cache memory read"
>> +        "EventCode": "0x36",
>> +        "EventName": "LL_CACHE_RD",
>> +        "BriefDescription": "Attributable Last level cache memory read"
>> +    },
>> +    {
>> +        "PublicDescription": "Last level cache miss, read"
>> +        "EventCode": "0x37",
>> +        "EventName": "LL_CACHE_MISS_RD",
>> +        "BriefDescription": "Last level cache miss, read"
>> +    },
> Missing comma at end of PublicDescription.
> 
>> +    },
>> +]
> Commas are not required.
> 
> Best Regards
> Shunsuke

Fine, I can fix those up and re-post today.

Thanks,
john