Received: by 2002:a05:6a10:8c0a:0:0:0:0 with SMTP id go10csp2076716pxb; Fri, 29 Jan 2021 12:28:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJxa5SNuiIPA1eEcSpqBXA46dC7g8t1kZApdQct7NofauiJnPeRyto7v7a8sJp3gqlVQtmb3 X-Received: by 2002:a17:907:9702:: with SMTP id jg2mr6524521ejc.48.1611952135964; Fri, 29 Jan 2021 12:28:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611952135; cv=none; d=google.com; s=arc-20160816; b=cahSx+Ty5mdW8J+i1BJGx9z/kXXHMldJFTRi8FvA64G5fDpaXZ+iODKNIA1jiXQj0h qZO4+elp2mEo8bjE/l2KvUBinugA63nWiEkPCwnsU27XE4cEWq9UF9h9kOsC2nhls2OW jbW6RzkS4ADs7G2KAOtVoyEyOoyOjI6obGKuRtT+ZBLKrtMl7YRnpgNMEif1hY3TiPQA dsVgPXuNjZiMwumA3nwZMR9CC9M45PS0doZjtdnAY+T1XmOmrb077R8bRaVEbs6ZbUd4 TGtxtrHk/xHvxkp/0CnHAN6Tn6Ho7FWqX7dHwmoQiFg8/mH0d+PY9+oD/UCLa2/+ke5a yr5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date; bh=fJAuYYZ37spjiLklg0C4vsVVyk94N2hmrlnKld9hx7k=; b=dBg2xkCPHHjYILSkGG+S6q1gOKviZRURYE/nuBJWhkDpu8ZpA3fToqASDqIpXCkcL8 wc/NxhkhhDPXlt1GxxjNiVbc2c73omn3Af3x42t6yr3+aoR5CM8uYsplrX6+BrlrgW5J ObnMGu//AZzz93jdIdle00Qvq68hr7D0zLo2BGPvh1afdIF973Wrc6XuOh3jsDxjJ1hH /cKy/w/oei+oV5M7ZohIc8trB9qu3f6RSC/8oCrGLMxm6R0lJOW+98ZyNHnI56m+1lxE EfnlGHAws8hfgElFfOk5/G29pDGhr8nq/jxvSR/yFLF/Mc7wE5we/EqaE5zeI+G5p1pH pyrQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dv5si5555374ejb.231.2021.01.29.12.28.31; Fri, 29 Jan 2021 12:28:55 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233250AbhA2U0f (ORCPT + 99 others); Fri, 29 Jan 2021 15:26:35 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:38822 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233365AbhA2UY0 (ORCPT ); Fri, 29 Jan 2021 15:24:26 -0500 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1l5aIo-003FK8-EP; Fri, 29 Jan 2021 21:23:34 +0100 Date: Fri, 29 Jan 2021 21:23:34 +0100 From: Andrew Lunn To: Mike Looijmans Cc: netdev@vger.kernel.org, "David S. Miller" , Heiner Kallweit , Jakub Kicinski , Russell King , linux-kernel@vger.kernel.org Subject: Re: [PATCH] net: mdiobus: Prevent spike on MDIO bus reset signal Message-ID: References: <20210126073337.20393-1-mike.looijmans@topic.nl> <1b153bce-a66a-45ee-a5c6-963ea6fb1c82.949ef384-8293-46b8-903f-40a477c056ae.7228ddf2-6794-42a0-8b0b-3821446cdb40@emailsignatures365.codetwo.com> <1b153bce-a66a-45ee-a5c6-963ea6fb1c82.0d2bd5fa-15cc-4b27-b94e-83614f9e5b38.7855d092-e2c3-4ba5-a029-2a0bbce637e1@emailsignatures365.codetwo.com> <956acc58-6ec8-c3d5-1310-7305c3b5a471@topic.nl> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <956acc58-6ec8-c3d5-1310-7305c3b5a471@topic.nl> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 28, 2021 at 09:45:41AM +0100, Mike Looijmans wrote: > Hi Andrew, > > Response below... Hi Mike Everybody here knows that top posting is evil, we don't do it. We expect the replay to be inline. > > Hi Mike > > > > Did you look at the per PHY reset? mdiobus_register_gpiod() gets the > > GPIO with GPIOD_OUT_LOW. mdiobus_register_device() then immediately > > sets it high. > > > > So it looks like it suffers from the same problem. > > Well, now that I have your attention... > > The per PHY reset was more broken It has history. It was designed to be used for PHYs which needed a reset after the clock was changed. It assumed the PHY would probe, which some do when held in reset. But the GPIO is not the only problem. Some PHYs need a regulator enabled, some need a clock enabled. The core has no idea what order to do this in. It should be the PHY driver that does this, since it should have knowledge of the PHY, and can do things in the correct order. But if the PHY does not respond, it is not discovered, and so the driver does not load. If that case, you can put the PHY ID into the compatible string, and the core will load the correct driver and probe it, allow it to turn on whatever it needs. This has been discussed a few times and this is what we decided on. Maybe we need to improve the documentation. Andrew