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[23.128.96.18]) by mx.google.com with ESMTP id jx2si5900516ejb.526.2021.01.30.01.01.38; Sat, 30 Jan 2021 01:02:04 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230208AbhA3JBC (ORCPT + 99 others); Sat, 30 Jan 2021 04:01:02 -0500 Received: from mga05.intel.com ([192.55.52.43]:10161 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230211AbhA3FHE (ORCPT ); Sat, 30 Jan 2021 00:07:04 -0500 IronPort-SDR: 8jjQKoEkz/vM7Oclm7ZUh8LFRMb+bvzUVw/YxVag8IxQd362jBfYQ2QG6wRCuCJBtKrMy7vRT4 2Z8XMxYRVrwg== X-IronPort-AV: E=McAfee;i="6000,8403,9879"; a="265339355" X-IronPort-AV: E=Sophos;i="5.79,387,1602572400"; d="scan'208";a="265339355" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2021 18:21:28 -0800 IronPort-SDR: TR4jCj3T9zEeNL6WrJYlPbpV64L0u7FPGzIR7L929+LVTVnNQEfZL/STuEyX5WkyYv20heFKkZ tpkP0AEAJIyQ== X-IronPort-AV: E=Sophos;i="5.79,387,1602572400"; d="scan'208";a="370626909" Received: from smtp.ostc.intel.com ([10.54.29.231]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2021 18:21:27 -0800 Received: from mtg-dev.jf.intel.com (mtg-dev.jf.intel.com [10.54.74.10]) by smtp.ostc.intel.com (Postfix) with ESMTP id C5E456368; Fri, 29 Jan 2021 18:21:27 -0800 (PST) Received: by mtg-dev.jf.intel.com (Postfix, from userid 1000) id BA634362DDA; Fri, 29 Jan 2021 18:21:27 -0800 (PST) From: mgross@linux.intel.com To: markgross@kernel.org, mgross@linux.intel.com, arnd@arndb.de, bp@suse.de, damien.lemoal@wdc.com, dragan.cvetic@xilinx.com, gregkh@linuxfoundation.org, corbet@lwn.net, palmerdabbelt@google.com, paul.walmsley@sifive.com, peng.fan@nxp.com, robh+dt@kernel.org, shawnguo@kernel.org, jassisinghbrar@gmail.com Cc: linux-kernel@vger.kernel.org, Daniele Alessandrelli , devicetree@vger.kernel.org Subject: [PATCH v3 04/34] dt-bindings: Add bindings for Keem Bay IPC driver Date: Fri, 29 Jan 2021 18:20:19 -0800 Message-Id: <20210130022124.65083-5-mgross@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210130022124.65083-1-mgross@linux.intel.com> References: <20210130022124.65083-1-mgross@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Daniele Alessandrelli Add DT binding documentation for the Intel Keem Bay IPC driver, which enables communication between the Computing Sub-System (CSS) and the Multimedia Sub-System (MSS) of the Intel Movidius SoC code named Keem Bay. Cc: Rob Herring Cc: devicetree@vger.kernel.org Reviewed-by: Mark Gross Signed-off-by: Daniele Alessandrelli --- .../bindings/soc/intel/intel,keembay-ipc.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml diff --git a/Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml b/Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml new file mode 100644 index 000000000000..586fe73f4cd4 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Intel Corporation +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/intel/intel,keembay-ipc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Keem Bay IPC + +maintainers: + - Daniele Alessandrelli + +description: + The Keem Bay IPC driver enables Inter-Processor Communication (IPC) with the + Visual Processor Unit (VPU) embedded in the Intel Movidius SoC code named + Keem Bay. + +properties: + compatible: + const: intel,keembay-ipc + + memory-region: + items: + - description: + Reserved memory region used by the CPU to allocate IPC packets. + - description: + Reserved memory region used by the VPU to allocate IPC packets. + + mboxes: + description: VPU IPC Mailbox. + +required: + - compatible + - memory-region + - mboxes + +additionalProperties: false + +examples: + - | + ipc { + compatible = "intel,keembay-ipc"; + memory-region = <&ipc_cpu_reserved>, <&ipc_vpu_reserved>; + mboxes = <&vpu_ipc_mbox 0>; + }; -- 2.17.1