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[23.128.96.18]) by mx.google.com with ESMTP id t19si3222052ejs.405.2021.02.01.15.26.25; Mon, 01 Feb 2021 15:26:50 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@intel-com.20150623.gappssmtp.com header.s=20150623 header.b="NAFm/mQN"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230092AbhBAXZc (ORCPT + 99 others); Mon, 1 Feb 2021 18:25:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230153AbhBAXZa (ORCPT ); Mon, 1 Feb 2021 18:25:30 -0500 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E4CACC061756 for ; Mon, 1 Feb 2021 15:24:49 -0800 (PST) Received: by mail-ej1-x62c.google.com with SMTP id r12so27030137ejb.9 for ; Mon, 01 Feb 2021 15:24:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=YHTyOhdcCBOSF1xYU4ShuqdV6jLXyArKbI9xZzFvPk0=; b=NAFm/mQNOdHOs7NCXjyi5VhvNLqf8pi87yCTAFIfRbho0uQixXrlQ1NHVypMfkg4VE AnHVfq00xVgGW4Oa0VrMNCfOENM9lWR3rdYBufl+aiYFrc+OcQmE0bSOiDyJh9N2+JOs JwUwgaS32yFr7JmbZNcG0nRI9ELxKwqN0aktrf0D/izeV6RR9vmbmW6WgGeSXNH5sqox X5EV6nHsR/GM11Ft5Tm1HMy0NY0xvvxdiQHqJXCxB4tNZNupEPw4DRYFpDOCkZj4GC/a VMT/r+LksMD1ugOpQ3spVRyENhXPswR6e2d0rCjXs90t+0BWzvBOBdPSF22xA5qQipYw YGtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=YHTyOhdcCBOSF1xYU4ShuqdV6jLXyArKbI9xZzFvPk0=; b=ckj7u1gbg5gzvsRnOqF8Y1jxmSdwVLV1Odgr9oiOVayWeChu7II6efbN9rzOcI/syF xiS9vNtP+SC/0XfD0m76DiPiY6a6PSvyiUnvmVX7H4G/ABONFT+DCe5klnBO2TMoOUC5 bH3gCO2WEVuvDe4jAmbzGQCW9EBJgMG6WlSuRgnSME5j5VC/kYCuC0HAAQZp7kiAjK7F /1CakbBkf32ixi2K42UZ7/3rIk3r13bEJOWG+1yYdS7gGMciu8tauxMByGTebYkTyVsQ Dz9cnHOoOeLChND66sn7VbpwrFV4XQwWMjvIVRCceIq+114qAyYdymywHU6zYjvdXptG +WiA== X-Gm-Message-State: AOAM532tBnaqHr7w+TFn0a2ml2qbTAQeBVTv5CL1DoLkwcsh5jiU3Qc4 hUztSysEWaK6wya59DviUcCWxfjxfqii4ccv6CeVRg== X-Received: by 2002:a17:906:e085:: with SMTP id gh5mr20079628ejb.418.1612221888522; Mon, 01 Feb 2021 15:24:48 -0800 (PST) MIME-Version: 1.0 References: <20210201223920.GA46282@bjorn-Precision-5520> In-Reply-To: <20210201223920.GA46282@bjorn-Precision-5520> From: Dan Williams Date: Mon, 1 Feb 2021 15:24:45 -0800 Message-ID: Subject: Re: [PATCH 04/15] PCI: Add pci_find_vsec_capability() to find a specific VSEC To: Bjorn Helgaas Cc: Gustavo Pimentel , Bjorn Helgaas , Linux PCI , Linux Kernel Mailing List , Vinod Koul , dmaengine@vger.kernel.org, Ben Widawsky Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org [ add Ben ] On Mon, Feb 1, 2021 at 2:39 PM Bjorn Helgaas wrote: > > [+cc Vinod, Dan, dmaengine] > > On Tue, Dec 15, 2020 at 06:30:13PM +0100, Gustavo Pimentel wrote: > > Add pci_find_vsec_capability() that crawls through the device config > > space searching in all Vendor-Specific Extended Capabilities for a > > particular capability ID. > > > > Vendor-Specific Extended Capability (VSEC) is a PCIe capability (acts > > like a wrapper) specified by PCI-SIG that allows the vendor to create > > their own and specific capability in the device config space. > > > > Signed-off-by: Gustavo Pimentel > > If you fix the below, feel free to add my > > Acked-by: Bjorn Helgaas > > Otherwise, I can take it myself. But that will be an ordering issue > in the merge window if you merge the rest of the series via another > tree. I wonder if this warrants and if you'd be willing to stand up a stable branch for just this commit for concerned parties to integrate, because CXL development should adopt it as well. > > > --- > > drivers/pci/pci.c | 29 +++++++++++++++++++++++++++++ > > include/linux/pci.h | 1 + > > include/uapi/linux/pci_regs.h | 5 +++++ > > 3 files changed, 35 insertions(+) > > > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > > index 6d4d5a2..235d0b2 100644 > > --- a/drivers/pci/pci.c > > +++ b/drivers/pci/pci.c > > @@ -623,6 +623,35 @@ u64 pci_get_dsn(struct pci_dev *dev) > > } > > EXPORT_SYMBOL_GPL(pci_get_dsn); > > > > +/** > > + * pci_find_vsec_capability - Find a vendor-specific extended capability > > + * @dev: PCI device to query > > + * @cap: vendor-specific capability id code > > s/id/ID/ > > > + * > > + * Returns the address of the vendor-specific structure that matches the > > + * requested capability id code within the device's PCI configuration space > > s/id/ID/ > > > + * or 0 if it does not find a match. > > + */ > > +int pci_find_vsec_capability(struct pci_dev *dev, int vsec_cap_id) > > +{ > > + u32 header; > > + int vsec; > > int vsec; > u32 header; > > since that's the order they're used. > > > + > > + vsec = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_VNDR); > > + while (vsec) { > > + if (pci_read_config_dword(dev, vsec + 0x4, > > s/0x4/PCI_VSEC_HDR/ > > > + &header) == PCIBIOS_SUCCESSFUL && > > + PCI_VSEC_CAP_ID(header) == vsec_cap_id) > > + break; > > return vsec; > > > + > > + vsec = pci_find_next_ext_capability(dev, vsec, > > + PCI_EXT_CAP_ID_VNDR); > > + } > > + > > + return vsec; > > return 0; > > > +} > > +EXPORT_SYMBOL_GPL(pci_find_vsec_capability); > > + > > static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) > > { > > int rc, ttl = PCI_FIND_CAP_TTL; > > diff --git a/include/linux/pci.h b/include/linux/pci.h > > index 22207a7..effecb0 100644 > > --- a/include/linux/pci.h > > +++ b/include/linux/pci.h > > @@ -1067,6 +1067,7 @@ int pci_find_capability(struct pci_dev *dev, int cap); > > int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); > > int pci_find_ext_capability(struct pci_dev *dev, int cap); > > int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); > > +int pci_find_vsec_capability(struct pci_dev *dev, int vsec_cap_id); > > int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); > > int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); > > struct pci_bus *pci_find_next_bus(const struct pci_bus *from); > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > > index a95d55f..f5d17be 100644 > > --- a/include/uapi/linux/pci_regs.h > > +++ b/include/uapi/linux/pci_regs.h > > @@ -730,6 +730,11 @@ > > #define PCI_EXT_CAP_DSN_SIZEOF 12 > > #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 > > > > +/* Vendor-Specific Extended Capabilities */ > > +#define PCI_VSEC_CAP_ID(header) (header & 0x0000ffff) > > +#define PCI_VSEC_CAP_REV(header) ((header >> 16) & 0xf) > > +#define PCI_VSEC_CAP_LEN(header) ((header >> 20) & 0xffc) > > Please put these next to the existing PCI_VSEC_HDR. > > Why does PCI_VSEC_CAP_LEN mask with 0xffc instead of 0xfff? I don't > see anything in the spec about VSEC Length having to be a multiple of > 4 (PCIe r5.0, sec 7.9.5.2). > > But you don't use this anyway, so I'd just drop it (and > PCI_VSEC_CAP_REV) altogether. > > > /* Advanced Error Reporting */ > > #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ > > #define PCI_ERR_UNC_UND 0x00000001 /* Undefined */ > > -- > > 2.7.4 > >