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[142.162.115.133]) by smtp.gmail.com with ESMTPSA id p22sm15466415qkk.128.2021.02.01.15.44.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 15:44:25 -0800 (PST) Received: from jgg by mlx with local (Exim 4.94) (envelope-from ) id 1l6iro-002MnI-P8; Mon, 01 Feb 2021 19:44:24 -0400 Date: Mon, 1 Feb 2021 19:44:24 -0400 From: Jason Gunthorpe To: "Tian, Kevin" Cc: "Song Bao Hua (Barry Song)" , "chensihang (A)" , Arnd Bergmann , Greg Kroah-Hartman , "linux-kernel@vger.kernel.org" , "iommu@lists.linux-foundation.org" , "linux-mm@kvack.org" , Zhangfei Gao , "Liguozhu (Kenneth)" , "linux-accelerators@lists.ozlabs.org" Subject: Re: [RFC PATCH v2] uacce: Add uacce_ctrl misc device Message-ID: <20210201234424.GI4718@ziepe.ca> References: <1611563696-235269-1-git-send-email-wangzhou1@hisilicon.com> <20210125154717.GW4605@ziepe.ca> <96b655ade2534a65974a378bb68383ee@hisilicon.com> <20210125231619.GY4605@ziepe.ca> <5f64a68042c64f37b5cba74028bd2189@hisilicon.com> <20210126011304.GZ4605@ziepe.ca> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jan 29, 2021 at 10:09:03AM +0000, Tian, Kevin wrote: > > SVA is not doom to work with IO page fault only. If we have SVA+pin, > > we would get both sharing address and stable I/O latency. > > Isn't it like a traditional MAP_DMA API (imply pinning) plus specifying > cpu_va of the memory pool as the iova? I think their issue is the HW can't do the cpu_va trick without also involving the system IOMMU in a SVA mode It really is something that belongs under some general /dev/sva as we talked on the vfio thread Jason