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From:   "Tian, Kevin" <kevin.tian@intel.com>
To:     Jason Gunthorpe <jgg@ziepe.ca>
CC:     "Song Bao Hua (Barry Song)" <song.bao.hua@hisilicon.com>,
        "chensihang (A)" <chensihang1@hisilicon.com>,
        Arnd Bergmann <arnd@arndb.de>,
        "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
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        Zhangfei Gao <zhangfei.gao@linaro.org>,
        "Liguozhu (Kenneth)" <liguozhu@hisilicon.com>,
        "linux-accelerators@lists.ozlabs.org" 
        <linux-accelerators@lists.ozlabs.org>
Subject: RE: [RFC PATCH v2] uacce: Add uacce_ctrl misc device
Thread-Topic: [RFC PATCH v2] uacce: Add uacce_ctrl misc device
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Date:   Tue, 2 Feb 2021 02:51:30 +0000
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> From: Jason Gunthorpe <jgg@ziepe.ca>
> Sent: Tuesday, February 2, 2021 7:44 AM
>=20
> On Fri, Jan 29, 2021 at 10:09:03AM +0000, Tian, Kevin wrote:
> > > SVA is not doom to work with IO page fault only. If we have SVA+pin,
> > > we would get both sharing address and stable I/O latency.
> >
> > Isn't it like a traditional MAP_DMA API (imply pinning) plus specifying
> > cpu_va of the memory pool as the iova?
>=20
> I think their issue is the HW can't do the cpu_va trick without also
> involving the system IOMMU in a SVA mode
>=20

This is the part that I didn't understand. Using cpu_va in a MAP_DMA
interface doesn't require device support. It's just an user-specified
address to be mapped into the IOMMU page table. On the other hand,
sharing CPU page table through a SVA interface for an usage where I/O=20
page faults must be completely avoided seems a misleading attempt.=20
Even if people do want this model (e.g. mix pinning+fault), it should be
a mm syscall as Greg pointed out, not specific to sva.

Thanks
Kevin