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[209.85.221.169]) by smtp.gmail.com with ESMTPSA id p9sm1139127vsq.6.2021.02.01.23.58.50 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Feb 2021 23:58:50 -0800 (PST) Received: by mail-vk1-f169.google.com with SMTP id g17so4591123vkk.5 for ; Mon, 01 Feb 2021 23:58:50 -0800 (PST) X-Received: by 2002:a1f:38c9:: with SMTP id f192mr3257323vka.24.1612252730254; Mon, 01 Feb 2021 23:58:50 -0800 (PST) MIME-Version: 1.0 References: <20210127172500.13356-1-andre.przywara@arm.com> <20210127172500.13356-7-andre.przywara@arm.com> <20210128101544.yyvrguk2jlgr4uwo@gilmour> In-Reply-To: <20210128101544.yyvrguk2jlgr4uwo@gilmour> From: Chen-Yu Tsai Date: Tue, 2 Feb 2021 15:58:38 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [linux-sunxi] Re: [PATCH v5 06/20] mfd: axp20x: Allow AXP chips without interrupt lines To: Andre Przywara , Lee Jones Cc: Maxime Ripard , Jernej Skrabec , Samuel Holland , Icenowy Zheng , Rob Herring , =?UTF-8?B?Q2zDqW1lbnQgUMOpcm9u?= , Shuosheng Huang , Yangtao Li , linux-arm-kernel , linux-kernel , linux-sunxi Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 28, 2021 at 6:15 PM Maxime Ripard wrote: > > On Wed, Jan 27, 2021 at 05:24:46PM +0000, Andre Przywara wrote: > > Currently the AXP chip requires to have its IRQ line connected to some > > interrupt controller, and will fail probing when this is not the case. > > > > On a new Allwinner SoC (H616) there is no NMI pin anymore, and at > > least one board does not connect the AXP's IRQ pin to anything else, > > so the interrupt functionality of the AXP chip is simply not available. > > > > Check whether the interrupt line number returned by the platform code is > > valid, before trying to register the irqchip. If not, we skip this > > registration, to avoid the driver to bail out completely. > > > > Signed-off-by: Andre Przywara > > Acked-by: Maxime Ripard Acked-by: Chen-Yu Tsai