Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932210AbWITS2Q (ORCPT ); Wed, 20 Sep 2006 14:28:16 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S932214AbWITS2Q (ORCPT ); Wed, 20 Sep 2006 14:28:16 -0400 Received: from iolanthe.rowland.org ([192.131.102.54]:1039 "HELO iolanthe.rowland.org") by vger.kernel.org with SMTP id S932210AbWITS2P (ORCPT ); Wed, 20 Sep 2006 14:28:15 -0400 Date: Wed, 20 Sep 2006 14:28:12 -0400 (EDT) From: Alan Stern X-X-Sender: stern@iolanthe.rowland.org To: Kernel development list Subject: Flushing writes to PCI devices Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 544 Lines: 12 I've heard that to insure proper synchronization it's necessary to flush MMIO writes (writel, writew, writeb) to PCI devices by reading from the same area. Is this equally true for I/O-space writes (inl, inw, inb)? What about configuration space writes (pci_write_config_dword etc.)? Alan Stern - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/