Received: by 2002:a05:6a10:8c0a:0:0:0:0 with SMTP id go10csp727831pxb; Tue, 2 Feb 2021 16:53:24 -0800 (PST) X-Google-Smtp-Source: ABdhPJx2sw1m+am2k+LbfxPB/tKaghN3OthaZnhbZIrwNrGEF6D3Parufqlo8TPCXBnEPGsBPjRj X-Received: by 2002:a17:906:b0c2:: with SMTP id bk2mr623394ejb.223.1612313604279; Tue, 02 Feb 2021 16:53:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612313604; cv=none; d=google.com; s=arc-20160816; b=gSknuvhhKmW8i6OpZWwvlEzdiICqTOe4fXcBVNIObmPvJvHYzM93I4Mxbu2f1qZG4l ulEqqoJypUNXzN8msntksHDEnehB46T8LvGAySv6+cPGTuXvELljr5KM2yueovVOlk/t A+RjyP5SPULrn4/h6hTHz6/cjcxjuJNxvqQk3L4B7YJIUeNBZlBQEp4/ot+Wk2i3NQXM HCHTsqxVDoRAeBaeQ534zk5x4H5suVf7yxW1VHg4veGzJP87NKic7X8pHAPt6832Ilwe kedTSe+Lfeg22kzfpO/UGqMON10bMO2FqLWdJfkKLFGsR+ReDdyJqcXUrtfB0/No2jC9 h3/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date:dkim-signature; bh=0kAvPlYbK2MoK6J2M4VB8aAoYja4iRJVl217ecqHS/M=; b=xH51zS/sattVXpKroObEOpTSq5ncLYMAJl8mswgaL1LWZ+i7+DmtzsYawaT0dYK9wV FexcDfJ9LtrcfEvQM1D3mkLvotKSBvOO03wk2SQChmPLg8PPyeHAOjc30mtSqlx0MvmL G9i2v8dqqBwgllUC68xD+T/PnEIguSMT2i3Ly+foi+peApV3RB30oiHqHoEpm0uSC/K0 K96RD8KxzDj8T84vjWD0riEJzAtdX4cF4m5T7rQ6khge+ujID3JAynejrB7py/wlPMpb kj4BfyPzjusv7p2zgbVijlDjQF/ldLygUVNjzdgVKliRc6wv5IWb2y7xKUk1ClZ6Uub7 1OkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TdhEHCPK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a10si221217edv.164.2021.02.02.16.52.59; Tue, 02 Feb 2021 16:53:24 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TdhEHCPK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233660AbhBBVvl (ORCPT + 99 others); Tue, 2 Feb 2021 16:51:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233477AbhBBVvh (ORCPT ); Tue, 2 Feb 2021 16:51:37 -0500 Received: from mail-oo1-xc2c.google.com (mail-oo1-xc2c.google.com [IPv6:2607:f8b0:4864:20::c2c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF741C06174A for ; Tue, 2 Feb 2021 13:50:56 -0800 (PST) Received: by mail-oo1-xc2c.google.com with SMTP id x23so5515100oop.1 for ; Tue, 02 Feb 2021 13:50:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=0kAvPlYbK2MoK6J2M4VB8aAoYja4iRJVl217ecqHS/M=; b=TdhEHCPKXXE10yUfrZQXXXYlAcYAm892Ap8QZ9AzljcQu07SHGtPQNNYh4Q/v8UYYk PiG4j2T7NHoMqPB+c49sk0YENnztQlT9XqeQ2395hb6rY5IEs1hQT8325ZkpwjtnD0LD Vwb8iIlhG8/SLn9tvFCsFcrmRKVpLkn2YwrhXeF78OkNw+se5xSHQHvNU3CsfgKG9FaV YTj35hwZuOWUyAJZ5e+Wy5z+o3F8CMc15IB60Zzzt6x8lLw1w1pKyKKhuu8IZkoQbFq+ kbiLZzLsWUDfraAPh5zgKYN28vNYG5WxwNeNf7ab6//sWGlal65rbmmLgoKH++R2kUTK 8D2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=0kAvPlYbK2MoK6J2M4VB8aAoYja4iRJVl217ecqHS/M=; b=V1IVnIdqVH92Qz3UuY+ZpF7Q+p8yrwDxjcPNQz3rb/h/UV9fEIw3NCPKIwpv4cNVkO gL1aTUHsmHDgUyWKC+pwWG1rIZQWesxHqvJI4hwhcfTP73xzj6rOYm77dJCz4Di67ZVt gQmiGgUMKlvjLm6MGhxSSRnUmLi84ZFSg9gzpO2Jo8Pn+wia7e3FO2Ga4tz4T4c4ySl/ TMBzetEH5wjHlqUSCOF33S43tgwsUfLRv/Bjp24XOGJPF2xxow6IB1aJec8kLy/EYrWp Z7Tpk0YzSmUbbn8q7wbyr3AMhAoo9sGd9jRyRn/jXju7id3OYnEEE/S/qGex7zrUMMs6 0kqA== X-Gm-Message-State: AOAM530n3nz4fBvJbKHbJpVU5Y5lwiC00lXKu2svpZuNQyYr1qcSugrt td1r3rC+zFIWogz+MrQeQgL0AQ== X-Received: by 2002:a4a:970b:: with SMTP id u11mr17039184ooi.79.1612302656147; Tue, 02 Feb 2021 13:50:56 -0800 (PST) Received: from builder.lan (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id c2sm19995ooo.17.2021.02.02.13.50.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Feb 2021 13:50:55 -0800 (PST) Date: Tue, 2 Feb 2021 15:50:53 -0600 From: Bjorn Andersson To: Rob Herring Cc: Dmitry Baryshkov , Bjorn Helgaas , Andy Gross , Arnd Bergmann , Greg Kroah-Hartman , Stanimir Varbanov , Lorenzo Pieralisi , Bjorn Helgaas , linux-arm-msm , Manivannan Sadhasivam , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "linux-kernel@vger.kernel.org" , PCI Subject: Re: [PATCH v2 3/5] pcie-qcom: provide a way to power up qca6390 chip on RB5 platform Message-ID: References: <20210129215024.GA113900@bjorn-Precision-5520> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue 02 Feb 15:37 CST 2021, Rob Herring wrote: > On Tue, Feb 2, 2021 at 1:48 PM Bjorn Andersson > wrote: > > > > On Sat 30 Jan 10:14 CST 2021, Dmitry Baryshkov wrote: > > > > > On Sat, 30 Jan 2021 at 06:53, Bjorn Andersson > > > wrote: > > > > > > > > On Fri 29 Jan 16:19 CST 2021, Dmitry Baryshkov wrote: > > > > > > > > > On Sat, 30 Jan 2021 at 00:50, Bjorn Helgaas wrote: > > > > > > > > > > > > On Fri, Jan 29, 2021 at 06:45:21AM +0300, Dmitry Baryshkov wrote: > > > > > > > On 28/01/2021 22:26, Rob Herring wrote: > > > > > > > > On Thu, Jan 28, 2021 at 11:52 AM Dmitry Baryshkov > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > Some Qualcomm platforms require to power up an external device before > > > > > > > > > probing the PCI bus. E.g. on RB5 platform the QCA6390 WiFi/BT chip needs > > > > > > > > > to be powered up before PCIe0 bus is probed. Add a quirk to the > > > > > > > > > respective PCIe root bridge to attach to the power domain if one is > > > > > > > > > required, so that the QCA chip is started before scanning the PCIe bus. > > > > > > > > > > > > > > > > This is solving a generic problem in a specific driver. It needs to be > > > > > > > > solved for any PCI host and any device. > > > > > > > > > > > > > > Ack. I see your point here. > > > > > > > > > > > > > > As this would require porting code from powerpc/spark of-pci code and > > > > > > > changing pcie port driver to apply power supply before bus probing happens, > > > > > > > I'd also ask for the comments from PCI maintainers. Will that solution be > > > > > > > acceptable to you? > > > > > > > > > > > > I can't say without seeing the code. I don't know enough about this > > > > > > scenario to envision how it might look. > > > > > > > > > > > > I guess the QCA6390 is a PCIe device? Why does it need to be powered > > > > > > up before probing? Shouldn't we get a link-up interrupt when it is > > > > > > powered up so we could probe it then? > > > > > > > > > > Not quite. QCA6390 is a multifunction device, with PCIe and serial > > > > > parts. It has internal power regulators which once enabled will > > > > > powerup the PCIe, serial and radio parts. There is no need to manage > > > > > regulators. Once enabled they will automatically handle device > > > > > suspend/resume, etc. > > > > > > > > > > > > > So what you're saying is that if either the PCI controller or bluetooth > > > > driver probes these regulators will be turned on, indefinitely? > > > > > > > > If so, why do we need a driver to turn them on, rather than just mark > > > > them as always-on? > > > > > > > > What's the timing requirement wrt regulators vs WL_EN/BT_EN? > > > > > > According to the documentation I have, they must be enabled right > > > after enabling powering the chip and they must stay enabled all the > > > time. > > > > > > > So presumably just marking these things always-on and flipping the GPIO > > statically won't be good enough due to the lack of control over the > > timing. > > > > This really do look like a simplified case of what we see with the > > PCIe attached modems, where similar requirements are provided, but also > > the ability to perform a device specific reset sequence in case the > > hardware has locked up. I'm slightly worried about the ability of > > extending your power-domain model to handle the restart operation > > though. > > I think this is an abuse of 'power-domains'. Just define the > regulators in both WiFi and BT nodes and have each driver enable them. > They're refcounted. If that's still not enough control over the power > sequencing, then create a 3rd entity to do it, but that doesn't need > to leak into DT. You already have all the information you need. > As Dmitry explained he still need to pull the two GPIOs high after enabling the regulators, but before scanning the PCI or serdev buses. I was thinking something along the lines you suggest, but I've not been able to come up with something that will guarantee the ordering of the events. Regards, Bjorn