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Date:   Tue, 02 Feb 2021 18:34:56 -0800 (PST)
Subject:     Re: [PATCH 2/3] riscv: Align on L1_CACHE_BYTES when STRICT_KERNEL_RWX
In-Reply-To: <20210129190038.1001626-2-atish.patra@wdc.com>
CC:     linux-kernel@vger.kernel.org, svancau@gmail.com,
        Atish Patra <Atish.Patra@wdc.com>, aou@eecs.berkeley.edu,
        Anup Patel <Anup.Patel@wdc.com>, ardb@kernel.org,
        kirill.shutemov@linux.intel.com, linux-riscv@lists.infradead.org,
        ndesaulniers@gooogle.com, Paul Walmsley <paul.walmsley@sifive.com>,
        zong.li@sifive.com
From:   Palmer Dabbelt <palmer@dabbelt.com>
To:     Atish Patra <Atish.Patra@wdc.com>
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On Fri, 29 Jan 2021 11:00:37 PST (-0800), Atish Patra wrote:
> From: Sebastien Van Cauwenberghe <svancau@gmail.com>
>
> Allows the sections to be aligned on smaller boundaries and
> therefore results in a smaller kernel image size.
>
> Signed-off-by: Sebastien Van Cauwenberghe <svancau@gmail.com>
> Reviewed-by: Atish Patra <atish.patra@wdc.com>
> ---
>  arch/riscv/include/asm/set_memory.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/include/asm/set_memory.h b/arch/riscv/include/asm/set_memory.h
> index 211eb8244a45..8b80c80c7f1a 100644
> --- a/arch/riscv/include/asm/set_memory.h
> +++ b/arch/riscv/include/asm/set_memory.h
> @@ -32,14 +32,14 @@ bool kernel_page_present(struct page *page);
>
>  #endif /* __ASSEMBLY__ */
>
> -#ifdef CONFIG_ARCH_HAS_STRICT_KERNEL_RWX
> +#ifdef CONFIG_STRICT_KERNEL_RWX
>  #ifdef CONFIG_64BIT
>  #define SECTION_ALIGN (1 << 21)
>  #else
>  #define SECTION_ALIGN (1 << 22)
>  #endif
> -#else /* !CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
> +#else /* !CONFIG_STRICT_KERNEL_RWX */
>  #define SECTION_ALIGN L1_CACHE_BYTES
> -#endif /* CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
> +#endif /* CONFIG_STRICT_KERNEL_RWX */
>
>  #endif /* _ASM_RISCV_SET_MEMORY_H */

Thanks, this is on fixes.