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References: <20210128153601.153126-1-alban.bedel@aerq.com> <CAMpxmJXACfOkRB6m-_n_EmUf=6zLjQAie-UcQw+MNr-rTRC2SA@mail.gmail.com>
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From:   Andy Shevchenko <andy.shevchenko@gmail.com>
Date:   Wed, 3 Feb 2021 12:12:52 +0200
Message-ID: <CAHp75VcPeJOrX0A3DLM8Z0v-H2xVd0TrrssEXe5ZMOFcspsrfQ@mail.gmail.com>
Subject: Re: [PATCH] gpio: pca953x: add support for open drain pins on PCAL6524
To:     Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc:     Alban Bedel <alban.bedel@aerq.com>,
        Linus Walleij <linus.walleij@linaro.org>,
        linux-gpio <linux-gpio@vger.kernel.org>,
        LKML <linux-kernel@vger.kernel.org>
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On Tue, Feb 2, 2021 at 1:45 PM Bartosz Golaszewski
<bgolaszewski@baylibre.com> wrote:
> On Thu, Jan 28, 2021 at 4:36 PM Alban Bedel <alban.bedel@aerq.com> wrote:
> >
> > From a quick glance at various datasheet the PCAL6524 seems to be the

Oh, even more typos

datasheets

> > only chip in this familly that support setting the drive mode of

supports

> > single pins. Other chips either don't support it at all, or can only
> > set the drive mode of whole banks, which doesn't map to the GPIO API.
> >
> > Add a new flag, PCAL6524, to mark chips that have the extra registers
> > needed for this feature. Then mark the needed register banks as
> > readable and writable, here we don't set OUT_CONF as writable,
> > although it is, as we only need to read it. Finally add a function
> > that configure the OUT_INDCONF register when the GPIO API set the
> > drive mode of the pins.

...

> Maybe call it PCAL6524_TYPE for consistency with the ones below?

In case you continue modifying this driver, I agree with Bart on
PCAL6524_TYPE along with new OF_6524() macro.

-- 
With Best Regards,
Andy Shevchenko