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[209.85.208.174]) by smtp.gmail.com with ESMTPSA id x19sm201546lfr.144.2021.02.03.02.44.19 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Feb 2021 02:44:20 -0800 (PST) Received: by mail-lj1-f174.google.com with SMTP id e18so27676285lja.12 for ; Wed, 03 Feb 2021 02:44:19 -0800 (PST) X-Received: by 2002:a2e:8616:: with SMTP id a22mr1383065lji.237.1612349059539; Wed, 03 Feb 2021 02:44:19 -0800 (PST) MIME-Version: 1.0 References: <20210121061804.26423-1-irui.wang@mediatek.com> In-Reply-To: <20210121061804.26423-1-irui.wang@mediatek.com> From: Alexandre Courbot Date: Wed, 3 Feb 2021 19:44:07 +0900 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 1/3] dt-bindings: media: mtk-vcodec: Separating mtk vcodec encoder node To: Irui Wang Cc: Hans Verkuil , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa , Hsin-Yi Wang , Maoguang Meng , Longfei Wang , Yunfei Dong , Linux Media Mailing List , devicetree , LKML , "moderated list:ARM/Mediatek SoC support" , srv_heupstream@mediatek.com, "moderated list:ARM/Mediatek SoC support" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 21, 2021 at 3:18 PM Irui Wang wrote: > > Updates binding document since the avc and vp8 hardware encoder in > MT8173 are now separated. Separate "mediatek,mt8173-vcodec-enc" to > "mediatek,mt8173-vcodec-vp8-enc" and "mediatek,mt8173-vcodec-avc-enc". > > Signed-off-by: Hsin-Yi Wang > Signed-off-by: Maoguang Meng > Signed-off-by: Irui Wang > > --- > .../bindings/media/mediatek-vcodec.txt | 58 ++++++++++--------- > 1 file changed, 31 insertions(+), 27 deletions(-) > > diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > index 8217424fd4bd..f85276e629bf 100644 > --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > @@ -4,7 +4,9 @@ Mediatek Video Codec is the video codec hw present in Mediatek SoCs which > supports high resolution encoding and decoding functionalities. > > Required properties: > -- compatible : "mediatek,mt8173-vcodec-enc" for MT8173 encoder > +- compatible : must be one of the following string: > + "mediatek,mt8173-vcodec-vp8-enc" for mt8173 vp8 encoder. > + "mediatek,mt8173-vcodec-avc-enc" for mt8173 avc encoder. IMHO "mediatek,mt8173-vcodec-enc-vp8" and "mediatek,mt8173-vcodec-enc-avc" would be more logical. Also to keep a bit of backward compatibility, shall we also allow "mediatek,mt8173-vcodec-enc" to be an alias for "mediatek,mt8173-vcodec-enc-avc"? The line above would become "mediatek,mt8173-vcodec-enc-avc" or "mediatek,mt8173-vcodec-enc" for mt8173 avc encoder. > "mediatek,mt8183-vcodec-enc" for MT8183 encoder. > "mediatek,mt8173-vcodec-dec" for MT8173 decoder. > - reg : Physical base address of the video codec registers and length of > @@ -13,10 +15,11 @@ Required properties: > - mediatek,larb : must contain the local arbiters in the current Socs. > - clocks : list of clock specifiers, corresponding to entries in > the clock-names property. > -- clock-names: encoder must contain "venc_sel_src", "venc_sel",, > - "venc_lt_sel_src", "venc_lt_sel", decoder must contain "vcodecpll", > - "univpll_d2", "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll", > - "venc_lt_sel", "vdec_bus_clk_src". > +- clock-names: > + avc venc must contain "venc_sel"; > + vp8 venc must contain "venc_lt_sel"; Can't we use "venc_sel" for both avc and vp8, since they are different nodes now? That way we can just say encoder must contain "venc_sel" which is clearer and also simpler on the code side. > + decoder must contain "vcodecpll", "univpll_d2", "clk_cci400_sel", > + "vdec_sel", "vdecpll", "vencpll", "venc_lt_sel", "vdec_bus_clk_src". > - iommus : should point to the respective IOMMU block with master port as > argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > for details. > @@ -80,14 +83,10 @@ vcodec_dec: vcodec@16000000 { > assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; > }; > > - vcodec_enc: vcodec@18002000 { > - compatible = "mediatek,mt8173-vcodec-enc"; > - reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/ > - <0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/ > - interrupts = , > - ; > - mediatek,larb = <&larb3>, > - <&larb5>; > +vcodec_enc: vcodec@18002000 { Let's use vcodec_enc_avc as a label? > + compatible = "mediatek,mt8173-vcodec-avc-enc"; > + reg = <0 0x18002000 0 0x1000>; > + interrupts = ; > iommus = <&iommu M4U_PORT_VENC_RCPU>, > <&iommu M4U_PORT_VENC_REC>, > <&iommu M4U_PORT_VENC_BSDMA>, > @@ -98,8 +97,20 @@ vcodec_dec: vcodec@16000000 { > <&iommu M4U_PORT_VENC_REF_LUMA>, > <&iommu M4U_PORT_VENC_REF_CHROMA>, > <&iommu M4U_PORT_VENC_NBM_RDMA>, > - <&iommu M4U_PORT_VENC_NBM_WDMA>, > - <&iommu M4U_PORT_VENC_RCPU_SET2>, > + <&iommu M4U_PORT_VENC_NBM_WDMA>; > + mediatek,larb = <&larb3>; > + mediatek,vpu = <&vpu>; > + clocks = <&topckgen CLK_TOP_VENC_SEL>; > + clock-names = "venc_sel"; > + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; > + }; > + > +vcodec_enc_lt: vcodec@19002000 { And here the label should probably be "vcodec_enc_vp8" for consistency. > + compatible = "mediatek,mt8173-vcodec-vp8-enc"; > + reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ > + interrupts = ; > + iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, > <&iommu M4U_PORT_VENC_REC_FRM_SET2>, > <&iommu M4U_PORT_VENC_BSDMA_SET2>, > <&iommu M4U_PORT_VENC_SV_COMA_SET2>, > @@ -108,17 +119,10 @@ vcodec_dec: vcodec@16000000 { > <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, > <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, > <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; > + mediatek,larb = <&larb5>; > mediatek,vpu = <&vpu>; > - clocks = <&topckgen CLK_TOP_VENCPLL_D2>, > - <&topckgen CLK_TOP_VENC_SEL>, > - <&topckgen CLK_TOP_UNIVPLL1_D2>, > - <&topckgen CLK_TOP_VENC_LT_SEL>; > - clock-names = "venc_sel_src", > - "venc_sel", > - "venc_lt_sel_src", > - "venc_lt_sel"; > - assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, > - <&topckgen CLK_TOP_VENC_LT_SEL>; > - assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>, > - <&topckgen CLK_TOP_UNIVPLL1_D2>; > + clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; > + clock-names = "venc_lt_sel"; > + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>; > }; > -- > 2.18.0 >