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From:   Kostya Porotchkin <kostap@marvell.com>
To:     Baruch Siach <baruch@tkos.co.il>
CC:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "andrew@lunn.ch" <andrew@lunn.ch>,
        "jaz@semihalf.com" <jaz@semihalf.com>,
        "gregory.clement@bootlin.com" <gregory.clement@bootlin.com>,
        "linux@armlinux.org.uk" <linux@armlinux.org.uk>,
        Nadav Haklai <nadavh@marvell.com>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "Stefan Chulski" <stefanc@marvell.com>,
        "mw@semihalf.com" <mw@semihalf.com>,
        "Ben Peled" <bpeled@marvell.com>,
        "sebastian.hesselbarth@gmail.com" <sebastian.hesselbarth@gmail.com>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>
Subject: RE: [EXT] Re: [PATCH 03/11] dts: mvebu: Add pin control definitions
 for SDIO interafce
Thread-Topic: [EXT] Re: [PATCH 03/11] dts: mvebu: Add pin control definitions
 for SDIO interafce
Thread-Index: AQHW+jEKQCswtMtvs0m9H80l6I30SKpGdXyAgAAKzWA=
Date:   Wed, 3 Feb 2021 14:39:57 +0000
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References: <20210203133138.10754-1-kostap@marvell.com>
 <20210203133138.10754-4-kostap@marvell.com> <87eehxcku8.fsf@tarshish>
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> -----Original Message-----
> From: Baruch Siach <baruch@tkos.co.il>
> Sent: Wednesday, February 3, 2021 16:01
> To: Kostya Porotchkin <kostap@marvell.com>
> Cc: linux-kernel@vger.kernel.org; devicetree@vger.kernel.org;
> andrew@lunn.ch; jaz@semihalf.com; gregory.clement@bootlin.com;
> linux@armlinux.org.uk; Nadav Haklai <nadavh@marvell.com>;
> robh+dt@kernel.org; Stefan Chulski <stefanc@marvell.com>;
> mw@semihalf.com; Ben Peled <bpeled@marvell.com>;
> sebastian.hesselbarth@gmail.com; linux-arm-kernel@lists.infradead.org
> Subject: [EXT] Re: [PATCH 03/11] dts: mvebu: Add pin control definitions =
for
> SDIO interafce
>=20
> External Email
>=20
> ----------------------------------------------------------------------
> Hi Konstantin,
>=20
> On Wed, Feb 03 2021, kostap@marvell.com wrote:
> > From: Konstantin Porotchkin <kostap@marvell.com>
> >
> > Add SDIO mode pin control configration for CP0 on A8K DB.
>=20
> This patch does not touch the A8K DB device-tree file.
>=20
[KP] Right, it changes the SoC DTSI. I missed it when ported the patch.
Will fix in the next version

Kosta

> baruch
>=20
> >
> > Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
> > ---
> >  arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 ++++++
> > arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 6 ++++++
> >  2 files changed, 12 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> > b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> > index 293403a1a333..179218774ba9 100644
> > --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> > +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
> > @@ -47,6 +47,12 @@
> >  	cp0_pinctrl: pinctrl {
> >  		compatible =3D "marvell,armada-7k-pinctrl";
> >
> > +		sdhci_pins: sdhi-pins {
> > +			marvell,pins =3D "mpp56", "mpp57", "mpp58",
> > +				       "mpp59", "mpp60", "mpp61", "mpp62";
> > +			marvell,function =3D "sdio";
> > +		};
> > +
> >  		nand_pins: nand-pins {
> >  			marvell,pins =3D
> >  			"mpp15", "mpp16", "mpp17", "mpp18", diff --git
> > a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> > b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> > index ee67c70bf02e..64100ae204da 100644
> > --- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> > +++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
> > @@ -70,6 +70,12 @@
> >  &cp0_syscon0 {
> >  	cp0_pinctrl: pinctrl {
> >  		compatible =3D "marvell,armada-8k-cpm-pinctrl";
> > +
> > +		sdhci_pins: sdhi-pins {
> > +			marvell,pins =3D "mpp56", "mpp57", "mpp58",
> > +				       "mpp59", "mpp60", "mpp61", "mpp62";
> > +			marvell,function =3D "sdio";
> > +		};
> >  	};
> >  };
>=20
>=20
> --
>                                                      ~. .~   Tk Open Syst=
ems
> =3D}------------------------------------------------ooO--U--Ooo----------=
--{=3D
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