Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932446AbWITXBy (ORCPT ); Wed, 20 Sep 2006 19:01:54 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S932460AbWITXBy (ORCPT ); Wed, 20 Sep 2006 19:01:54 -0400 Received: from mtagate4.uk.ibm.com ([195.212.29.137]:36421 "EHLO mtagate4.uk.ibm.com") by vger.kernel.org with ESMTP id S932446AbWITXBw (ORCPT ); Wed, 20 Sep 2006 19:01:52 -0400 In-Reply-To: <1158749069.7705.9.camel@localhost.localdomain> Subject: Re: [PATCH] Linux Kernel Markers To: Alan Cox Cc: Andrew Morton , Mathieu Desnoyers , "Frank Ch. Eigler" , Greg Kroah-Hartman , Christoph Hellwig , Jes Sorensen , karim@opersys.com, Paul Mundt , linux-kernel , ltt-dev@shafik.org, Martin Bligh , Michel Dagenais , Ingo Molnar , prasanna@in.ibm.com, systemtap@sources.redhat.com, Thomas Gleixner , William Cohen , Tom Zanussi X-Mailer: Lotus Notes Release 7.0.1 July 07, 2006 Message-ID: From: Richard J Moore Date: Thu, 21 Sep 2006 00:00:41 +0100 X-MIMETrack: Serialize by Router on D06ML065/06/M/IBM(Release 6.5.5HF607 | June 26, 2006) at 21/09/2006 00:03:00 MIME-Version: 1.0 Content-type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1386 Lines: 35 Alan Cox wrote on 20/09/2006 11:44:29: > Ar Maw, 2006-09-19 am 20:52 -0400, ysgrifennodd Karim Yaghmour: > > a) the errata & a possible thread having an IP leading back within (not > > at the start of) the range to be replaced. > > b) the errata & replacing single instruction with single instruction of > > same size. > > Intel don't distinguish. Richard's reply later in the thread answers a > lot more including what Intels architecture team said about int3 being a > specific safe case for soem reason > > > I was vaguely aware of the issue on x86. Do you know if this applies the > > same on other achitectures? > > I wouldn't know. It can for another reason - score-boarding: that's where a byte being stored assumes intermediate values due to the bits not being set simultaneously. Generally this doesn't cause a problem because data across processors is serialised for update by mutexes. However, when applied to code all sorts of interesting instructions can execute before the bits settle down. I haven't heard of this troubling Intel, but it does occur on some current architectures. Richard - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/