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From:   Marcin Wojtas <mw@semihalf.com>
Date:   Fri, 5 Feb 2021 10:33:18 +0100
Message-ID: <CAPv3WKdvzZm2qpaNBr7zCzqnzuadhreTe-2E=91TxG2zGQ692A@mail.gmail.com>
Subject: Re: [EXT] Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI settings
To:     Kostya Porotchkin <kostap@marvell.com>
Cc:     Russell King - ARM Linux admin <linux@armlinux.org.uk>,
        Baruch Siach <baruch@tkos.co.il>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "andrew@lunn.ch" <andrew@lunn.ch>,
        "jaz@semihalf.com" <jaz@semihalf.com>,
        "gregory.clement@bootlin.com" <gregory.clement@bootlin.com>,
        Nadav Haklai <nadavh@marvell.com>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        Stefan Chulski <stefanc@marvell.com>,
        Ben Peled <bpeled@marvell.com>,
        "sebastian.hesselbarth@gmail.com" <sebastian.hesselbarth@gmail.com>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>
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Hi Kosta,

Let me chime in.

=C5=9Br., 3 lut 2021 o 17:57 Kostya Porotchkin <kostap@marvell.com> napisa=
=C5=82(a):
>
> Hello, Russell,
> I agree that this patch needs rework.
> I will definitely do it and issue a new version.
>
> > On Wed, Feb 03, 2021 at 02:50:45PM +0000, Kostya Porotchkin wrote:
> > > [KP] So for older systems this "slow mode" parameter could be set on =
the
> > board level.
> > > When it is set in ap80x,dtsi file it downgrades all systems to HS-SDR=
52, even
> > if they support HS400 on AP side.
> > > MacchiatoBIN AP eMMC is connected to 3.3v regulator and has "no-1-8-v=
"
> > flag set, so it should remain in low speed anyway.
> >
> > Your reasoning does not make sense.
> >
> > The ap80x.dtsi file does not specify "marvell,xenon-phy-slow-mode".
> > It is not specified at this level. It is already specified at board lev=
el.
> [KP] it does. In current armada-ap80x.dtsi File this specification is on =
row 260:
>                         ap_sdhci0: sdhci@6e0000 {
>                                 compatible =3D "marvell,armada-ap806-sdhc=
i";
>                                 reg =3D <0x6e0000 0x300>;
>                                 interrupts =3D <GIC_SPI 16 IRQ_TYPE_LEVEL=
_HIGH>;
>                                 clock-names =3D "core";
>                                 clocks =3D <&ap_clk 4>;
>                                 dma-coherent;
>                                 marvell,xenon-phy-slow-mode;
>                                 status =3D "disabled";
>                         };
> So I would like to remove this row.
>
> > Given that Macchiatobin will still use slow mode, why remove the
> > marvell,xenon-phy-slow-mode property from this file?
> [KP] Agree, I will keep this property in Macchiatobin DTS file.
>

Please do it another way around.
1. We need to leave the device tree bindings intact as much as
possible -  specifically for Armada 7k8k changes in this area have
been causing enough problems in the past, breaking compatibility
between kernel revisions. Moving the property to board level can be
good here, but forces all other board dts files to adjust.
Unfortunately Linux is a source of truth for the arm64 device tree
bindings, but please note other OS's use those files as well - let's
minimize the impact for existing HW and drivers.

2. What I propose is to remove `marvell,xenon-phy-slow-mode` from
armada-ap80x.dtsi and add below in armada-ap806.dtsi:
&ap_sdhci0 {
         marvell,xenon-phy-slow-mode;
 };

This way AP807 becomes free from the unwanted slow mode setting. Also
any user of Armada 7k8k the B0 revision can add below to the board
file:

&ap_sdhci0 {
+      /delete-property/marvell,xenon-phy-slow-mode;
 };

3. Contrary to the SDK version, sdhci-xenon.c is not capable of
checking the SoC revision. HS200 is disabled for all versions of AP806
there - I believe this place requires revisiting, to start relying
explicitly on the `marvell,xenon-phy-slow-mode` setting, rather than
the compatible string. I can handle this one.

4. Please move armada-8040-db.dts changes to a separate patch, please.

Thanks,
Marcin


> >
> > Also, if you're upgrading ap80x.dtsi to use a bus-width of 8, why keep =
the bus-
> > width specifier of 8 in the board files?
> [KP] The bus width is updated in A8040 DB DTS. This board utilizes 8-bit =
interface.
> The armada-ap80x.dtsi file does not specifies the bus width since it is b=
oard-specific.
>
> >
> > This patch just doesn't make sense, and your responses to our points se=
em to
> > add to the confusion.
> [KP] I am sorry about it. Hope my last response clarifies it.
>
> Kosta
> >
> > --
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> > FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!