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Subject: Re: [PATCH v19 08/25] x86/mm: Introduce _PAGE_COW
To:     Dave Hansen <dave.hansen@intel.com>,
        Kees Cook <keescook@chromium.org>
Cc:     x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
        Thomas Gleixner <tglx@linutronix.de>,
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        Arnd Bergmann <arnd@arndb.de>,
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        Balbir Singh <bsingharora@gmail.com>,
        Borislav Petkov <bp@alien8.de>,
        Cyrill Gorcunov <gorcunov@gmail.com>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        Eugene Syromiatnikov <esyr@redhat.com>,
        Florian Weimer <fweimer@redhat.com>,
        "H.J. Lu" <hjl.tools@gmail.com>, Jann Horn <jannh@google.com>,
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        Randy Dunlap <rdunlap@infradead.org>,
        "Ravi V. Shankar" <ravi.v.shankar@intel.com>,
        Vedvyas Shanbhogue <vedvyas.shanbhogue@intel.com>,
        Dave Martin <Dave.Martin@arm.com>,
        Weijiang Yang <weijiang.yang@intel.com>,
        Pengfei Xu <pengfei.xu@intel.com>
References: <20210203225547.32221-1-yu-cheng.yu@intel.com>
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 <202102041215.B54FCA552F@keescook>
 <2e43bf0b-e1a9-99f6-8d5d-d6e6886b4217@intel.com>
From:   "Yu, Yu-cheng" <yu-cheng.yu@intel.com>
Message-ID: <7381d8c1-5e1c-2667-7cb8-0a99f2c79b6d@intel.com>
Date:   Fri, 5 Feb 2021 10:41:52 -0800
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On 2/4/2021 12:27 PM, Dave Hansen wrote:
> On 2/4/21 12:19 PM, Kees Cook wrote:
>>> (e) A page where the processor observed a Write=1 PTE, started a write, set
>>>      Dirty=1, but then observed a Write=0 PTE.  That's possible today, but
>>>      will not happen on processors that support shadow stack.
>> What happens for "e" with/without CET? It sounds like direct writes to
>> such pages will be (correctly) rejected by the MMU?
> 
> A page fault would be generated regardless of CET support.
> 
> If CET were not around, the fault would be reported as a present, write
> fault.
> 
> If this happened and CET were around (which shouldn't happen in
> practice, it means we have a hardware issue) a page fault exception is
> generated. 

Thanks for the clarification.  With or without CET, direct write to 
Write=0, Dirty=1 PTE triggers page fault.

> Yu-cheng, I'm not sure there's enough debugging around to
> tell us if this happens.  Would we even notice?

That potential hardware issue is, on a CET-capable system, a processor 
writes to a Write=1, Dirty=0 page, and then observes the PTE is Write=0, 
Dirty=1.  Let me think about it...

Thanks!

--
Yu-cheng