To: "Bryan O'Sullivan" <bos@serpentine.com>
Cc: Bill Waddington <william.waddington@beezmo.com>,
       linux-kernel@vger.kernel.org
Subject: Re: Flushing writes to PCI devices
References: <fa.gbsNbubc34pqWPOxWCntrwUyt68@ifi.uio.no>
	<Pine.LNX.4.44L0.0609201423480.7265-100000@iolanthe.rowland.org>
	<fa.V4O8HKrhUddxYm5+ixVbyZzPybE@ifi.uio.no>
	<6263h29e4o17ok032m8rv11p4u6547ngk0@4ax.com>
	<1158862442.29551.22.camel@sardonyx>
From: Roland Dreier <rdreier@cisco.com>
Date: Thu, 21 Sep 2006 13:56:59 -0700
In-Reply-To: <1158862442.29551.22.camel@sardonyx> (Bryan O'Sullivan's message of "Thu, 21 Sep 2006 11:14:02 -0700")
Message-ID: <adavenhgcpw.fsf@cisco.com>
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    Bryan> Yes.  If your device requires that writes to some locations
    Bryan> in MMIO space be performed in a specific order, you must
    Bryan> explicitly do this in your driver.  Intel CPUs will flush
    Bryan> posted writes out of order, for example.

Really?  Just normal posted PCI writes without using MTRRs or
write-combining or anything like that?

That doesn't seem right to me, and I would expect all sorts of things
to break if it were true.

 - R.
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