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[23.128.96.18]) by mx.google.com with ESMTP id t16si8412622edi.281.2021.02.05.16.05.31; Fri, 05 Feb 2021 16:05:55 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Jmz7cvf5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231128AbhBFACI (ORCPT + 99 others); Fri, 5 Feb 2021 19:02:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231486AbhBENtK (ORCPT ); Fri, 5 Feb 2021 08:49:10 -0500 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 798F8C06178B for ; Fri, 5 Feb 2021 05:48:09 -0800 (PST) Received: by mail-wr1-x429.google.com with SMTP id d16so7695967wro.11 for ; Fri, 05 Feb 2021 05:48:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=b5Gt7lm7HDFnKYf2RrWhjZE+siO4dcLCTKmn9MIyd28=; b=Jmz7cvf53TjCwGxQHJHpsHhluwKoKsW3viJc5Y8zvSIecn+748ZRpAoe5PqRxJZt8w rTgZsaEPI5cjxNaMnArIgWgcCM9mV0CGhOHtYEDUH4H4+I6hxx5D55dBd3//G2HTrYQW Xa5KuupgmPF17JaHIEkxdFpNkycMdf16pWqxm/1J//nluKu//pehprHvxiovF/43U1rt g+wdOM9fd+nBHCmJySychS2ArSgVi0HMAn5Q2J8WraMm0U/nI5Gzq837tdQ12dl9TCBj +5W12Zbl5nJ7K0kehzObfdw1gRKuH5RrThAfjxYPE29Ud1aUyMKRfZSEC/oi3x4Rg5m/ YLOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=b5Gt7lm7HDFnKYf2RrWhjZE+siO4dcLCTKmn9MIyd28=; b=Z/6Ix6M0JpoD9v7gYbvOO5+S/xkAgtPrDixwdgNenMe1nTFPH3EznSC1UCNUFGs0cp Y2u7BZ7970SdhHSGv2fBlAfH3ASTyE1oNUCpPGwL7JziN1BhaJXXo69sWoqEL9dF4Tc8 XkOzwG2FuqJxNXRVX+wzcoiOwzaL2lvD/FYXqdQjO1+ZrD+sZoXPKnY8Ydehpocu1FrE gqK7D1cKbsbaOnOEbXqk2MQ9Cb451JbpxOpIayQtTuzwgqfxqODhbhETooOJEDhjEazL iHMOms/ouUTe0/3WBbJCGQdoe2DQD0zxhDhoqgfjQQTbZd4QstXsZUo6Fk412zqF9I0G 0vrQ== X-Gm-Message-State: AOAM530uBffdla9aDRSZI9VoUvvllev7gyStbeWkqN+/t6cj7MNGFkA9 FNxUKwFUZROTDphR3wdtQp7M9mU664MiN3nSJhFRYw== X-Received: by 2002:a5d:6685:: with SMTP id l5mr5068041wru.176.1612532888143; Fri, 05 Feb 2021 05:48:08 -0800 (PST) MIME-Version: 1.0 References: <20210202163842.134734-1-leo.yan@linaro.org> <20210202163842.134734-3-leo.yan@linaro.org> <3c0a0641-a375-c7c3-d72d-e1d626e60ad6@arm.com> In-Reply-To: <3c0a0641-a375-c7c3-d72d-e1d626e60ad6@arm.com> From: Mike Leach Date: Fri, 5 Feb 2021 13:47:57 +0000 Message-ID: Subject: Re: [PATCH v2 2/7] coresight: etm-perf: Support PID tracing for kernel at EL2 To: Suzuki K Poulose Cc: Leo Yan , Arnaldo Carvalho de Melo , Mathieu Poirier , Jonathan Corbet , Alexander Shishkin , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Mark Rutland , Jiri Olsa , Namhyung Kim , Daniel Kiss , Denis Nikitin , Coresight ML , linux-arm-kernel , "open list:DOCUMENTATION" , Linux Kernel Mailing List , Al Grant Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2 Feb 2021 at 23:06, Suzuki K Poulose wrote: > > On 2/2/21 4:38 PM, Leo Yan wrote: > > From: Suzuki K Poulose > > > > When the kernel is running at EL2, the PID is stored in CONTEXTIDR_EL2. > > So, tracing CONTEXTIDR_EL1 doesn't give us the pid of the process. > > Thus we should trace the VMID with VMIDOPT set to trace CONTEXTIDR_EL2 > > instead of CONTEXTIDR_EL1. Given that we have an existing config > > option "contextid" and this will be useful for tracing virtual machines > > (when we get to support virtualization). > > > > So instead, this patch extends option CTXTID with an extra bit > > ETM_OPT_CTXTID2 (bit 15), thus on an EL2 kernel, we will have another > > bit available for the perf tool: ETM_OPT_CTXTID is for kernel running in > > EL1, ETM_OPT_CTXTID2 is used when kernel runs in EL2 with VHE enabled. > > > > The tool must be backward compatible for users, i.e, "contextid" today > > traces PID and that should remain the same; for this purpose, the perf > > tool is updated to automatically set corresponding bit for the > > "contextid" config, therefore, the user doesn't have to bother which EL > > the kernel is running. > > > > i.e, perf record -e cs_etm/contextid/u -- > > > > will always do the "pid" tracing, independent of the kernel EL. > > > > The driver parses the format "contextid", which traces CONTEXTIDR_EL1 > > for ETM_OPT_CTXTID (on EL1 kernel) and traces CONTEXTIDR_EL2 for > > ETM_OPT_CTXTID2 (on EL2 kernel). > > > > Besides the enhancement for format "contexid", extra two formats are > > introduced: "contextid1" and "contextid2". This considers to support > > tracing both CONTEXTIDR_EL1 and CONTEXTIDR_EL2 when the kernel is > > running at EL2. Finally, the PMU formats are defined as follow: > > > > "contextid1": Available on both EL1 kernel and EL2 kernel. When the > > kernel is running at EL1, "contextid1" enables the PID > > tracing; when the kernel is running at EL2, this enables > > tracing the PID of guest applications. > > > > "contextid2": Only usable when the kernel is running at EL2. When > > selected, enables PID tracing on EL2 kernel. > > > > "contextid": Will be an alias for the option that enables PID > > tracing. I.e, > > contextid == contextid1, on EL1 kernel. > > contextid == contextid2, on EL2 kernel. > > > > Cc: Mathieu Poirier > > Cc: Al Grant > > Cc: Mike Leach > > Cc: Leo Yan > > Signed-off-by: Suzuki K Poulose > > You may add the following line here : > > [ Added two config formats: contextid1, contextid2 ] > > > Signed-off-by: Leo Yan > > The patch as such looks good to me. > > Suzuki Reviewed-by: Mike Leach -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK