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[23.128.96.18]) by mx.google.com with ESMTP id s8si6332773edd.534.2021.02.05.20.32.30; Fri, 05 Feb 2021 20:32:54 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231438AbhBFEbZ (ORCPT + 99 others); Fri, 5 Feb 2021 23:31:25 -0500 Received: from mga17.intel.com ([192.55.52.151]:55065 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231842AbhBFDRc (ORCPT ); Fri, 5 Feb 2021 22:17:32 -0500 IronPort-SDR: MLxop3mJlIPAFCT1lW53CZTIYE/BCcxtRzw7wfvBiKie2Q8x57QfD3Xdki4z7dTPd3vcF9tMWx LQXONaBLjDMQ== X-IronPort-AV: E=McAfee;i="6000,8403,9886"; a="161252116" X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="161252116" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 14:52:08 -0800 IronPort-SDR: 3j72SscZXefY/+QJIEX2k2peUeynHayBrrCKbTGML9T1XCZdr3XJ/dsuIiNbIyn3HIiJCM8PRl LSgfOApEsF3g== X-IronPort-AV: E=Sophos;i="5.81,156,1610438400"; d="scan'208";a="397637779" Received: from smtp.ostc.intel.com ([10.54.29.231]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 14:52:08 -0800 Received: from mtg-dev.jf.intel.com (mtg-dev.jf.intel.com [10.54.74.10]) by smtp.ostc.intel.com (Postfix) with ESMTP id 10F356369; Fri, 5 Feb 2021 14:52:08 -0800 (PST) Received: by mtg-dev.jf.intel.com (Postfix, from userid 1000) id 00C77362642; Fri, 5 Feb 2021 14:52:07 -0800 (PST) From: mgross@linux.intel.com To: markgross@kernel.org, mgross@linux.intel.com, arnd@arndb.de, bp@suse.de, damien.lemoal@wdc.com, dragan.cvetic@xilinx.com, gregkh@linuxfoundation.org, corbet@lwn.net, palmerdabbelt@google.com, paul.walmsley@sifive.com, peng.fan@nxp.com, robh+dt@kernel.org, shawnguo@kernel.org, jassisinghbrar@gmail.com Cc: linux-kernel@vger.kernel.org, Daniele Alessandrelli , devicetree@vger.kernel.org Subject: [PATCH v5 02/34] dt-bindings: mailbox: Add Intel VPU IPC mailbox bindings Date: Fri, 5 Feb 2021 14:51:32 -0800 Message-Id: <20210205225204.32902-3-mgross@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210205225204.32902-1-mgross@linux.intel.com> References: <20210205225204.32902-1-mgross@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Daniele Alessandrelli Add bindings for the Intel VPU IPC mailbox driver. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Daniele Alessandrelli Signed-off-by: Mark Gross --- .../mailbox/intel,vpu-ipc-mailbox.yaml | 69 +++++++++++++++++++ MAINTAINERS | 6 ++ 2 files changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml new file mode 100644 index 000000000000..923a6d619a64 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2020 Intel Corporation +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mailbox/intel,vpu-ipc-mailbox.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel VPU IPC mailbox + +maintainers: + - Daniele Alessandrelli + +description: | + Intel VPU SoCs like Keem Bay have hardware FIFOs to enable Inter-Processor + Communication (IPC) between the CPU and the VPU. + + Specifically, there is one HW FIFO for the CPU (aka Application Processor - + AP) and one for the VPU. Each FIFO can hold 128 entries of 32 bits each. A + "FIFO-not-empty" interrupt is raised every time there is at least a message + in the FIFO. The CPU FIFO raises interrupts to the CPU, while the VPU FIFO + raises interrupts to VPU. When the CPU wants to send a message to the VPU it + writes to the VPU FIFO, similarly, when the VPU want to send a message to the + CPU, it writes to the CPU FIFO. + + Refer to ./mailbox.txt for generic information about mailbox device-tree + bindings. + +properties: + compatible: + const: intel,vpu-ipc-mailbox + + reg: + items: + - description: The CPU FIFO registers + - description: The VPU FIFO registers + + reg-names: + items: + - const: cpu_fifo + - const: vpu_fifo + + interrupts: + items: + - description: CPU FIFO-not-empty interrupt + + "#mbox-cells": + const: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + #include + vpu_ipc_mailbox@203300f0 { + compatible = "intel,vpu-ipc-mailbox"; + #mbox-cells = <1>; + reg = <0x203300f0 0x310>, + <0x208200f0 0x310>; + reg-names = "cpu_fifo", "vpu_fifo"; + interrupts = ; + }; diff --git a/MAINTAINERS b/MAINTAINERS index d3e847f7f3dc..6dbecebfcfad 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9179,6 +9179,12 @@ L: platform-driver-x86@vger.kernel.org S: Maintained F: drivers/platform/x86/intel-vbtn.c +INTEL VPU IPC MAILBOX +M: Daniele Alessandrelli +M: Mark Gross +S: Supported +F: Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml + INTEL WIRELESS 3945ABG/BG, 4965AGN (iwlegacy) M: Stanislaw Gruszka L: linux-wireless@vger.kernel.org -- 2.17.1