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Date:   Sat, 6 Feb 2021 15:40:04 -0800
From:   Jakub Kicinski <kuba@kernel.org>
To:     <stefanc@marvell.com>
Cc:     <netdev@vger.kernel.org>, <thomas.petazzoni@bootlin.com>,
        <davem@davemloft.net>, <nadavh@marvell.com>,
        <ymarkman@marvell.com>, <linux-kernel@vger.kernel.org>,
        <linux@armlinux.org.uk>, <mw@semihalf.com>, <andrew@lunn.ch>,
        <rmk+kernel@armlinux.org.uk>, <atenart@kernel.org>,
        Konstantin Porotchkin <kostap@marvell.com>
Subject: Re: [PATCH v8 net-next 02/15] dts: marvell: add CM3 SRAM memory to
 cp11x ethernet device tree
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In-Reply-To: <1612629961-11583-3-git-send-email-stefanc@marvell.com>
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        <1612629961-11583-3-git-send-email-stefanc@marvell.com>
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On Sat, 6 Feb 2021 18:45:48 +0200 stefanc@marvell.com wrote:
> From: Konstantin Porotchkin <kostap@marvell.com>
> 
> CM3 SRAM address space would be used for Flow Control configuration.
> 
> Signed-off-by: Stefan Chulski <stefanc@marvell.com>
> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

Isn't there are requirement to CC the DT mailing list and Rob on all
device tree patches?  Maybe someone can clarify I know it's required
when adding bindings..