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Sun, 7 Feb 2021 20:58:52 +0800 From: Jitao Shi To: Chun-Kuang Hu , Philipp Zabel CC: , , , , , , , , , , , , , , , , Jitao Shi Subject: [PATCH 1/3] drm/mediatek: mtk_dpi: Add check for max clock rate in mode_valid Date: Sun, 7 Feb 2021 20:58:48 +0800 Message-ID: <20210207125850.155979-2-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210207125850.155979-1-jitao.shi@mediatek.com> References: <20210207125850.155979-1-jitao.shi@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: C54BD919B85FF8900CD6F4AF46479ECE6B27F0B8370B8FE00BFC5F265680C9362000:8 X-MTK: N Content-Transfer-Encoding: base64 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org QWRkIHBlci1wbGF0Zm9ybSBtYXggY2xvY2sgcmF0ZSBjaGVjayBpbiBtdGtfZHBpX2JyaWRnZV9t b2RlX3ZhbGlkLg0KDQpTaWduZWQtb2ZmLWJ5OiBKaXRhbyBTaGkgPGppdGFvLnNoaUBtZWRpYXRl ay5jb20+DQotLS0NCiBkcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RwaS5jIHwgMTcgKysr KysrKysrKysrKysrKysNCiAxIGZpbGUgY2hhbmdlZCwgMTcgaW5zZXJ0aW9ucygrKQ0KDQpkaWZm IC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcGkuYyBiL2RyaXZlcnMvZ3B1 L2RybS9tZWRpYXRlay9tdGtfZHBpLmMNCmluZGV4IDUyZjExYTYzYTMzMC4uZmZhNGEwZjE5ODlm IDEwMDY0NA0KLS0tIGEvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcGkuYw0KKysrIGIv ZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcGkuYw0KQEAgLTExOCw2ICsxMTgsNyBAQCBz dHJ1Y3QgbXRrX2RwaV95Y19saW1pdCB7DQogc3RydWN0IG10a19kcGlfY29uZiB7DQogCXVuc2ln bmVkIGludCAoKmNhbF9mYWN0b3IpKGludCBjbG9jayk7DQogCXUzMiByZWdfaF9mcmVfY29uOw0K Kwl1MzIgbWF4X2Nsb2NrX2toejsNCiAJYm9vbCBlZGdlX3NlbF9lbjsNCiB9Ow0KIA0KQEAgLTU1 NSw5ICs1NTYsMjIgQEAgc3RhdGljIHZvaWQgbXRrX2RwaV9icmlkZ2VfZW5hYmxlKHN0cnVjdCBk cm1fYnJpZGdlICpicmlkZ2UpDQogCW10a19kcGlfc2V0X2Rpc3BsYXlfbW9kZShkcGksICZkcGkt Pm1vZGUpOw0KIH0NCiANCitzdGF0aWMgZW51bSBkcm1fbW9kZV9zdGF0dXMNCittdGtfZHBpX2Jy aWRnZV9tb2RlX3ZhbGlkKHN0cnVjdCBkcm1fYnJpZGdlICpicmlkZ2UsDQorCQkJICBjb25zdCBz dHJ1Y3QgZHJtX2Rpc3BsYXlfbW9kZSAqbW9kZSkNCit7DQorCXN0cnVjdCBtdGtfZHBpICpkcGkg PSBicmlkZ2VfdG9fZHBpKGJyaWRnZSk7DQorDQorCWlmIChkcGktPmNvbmYtPm1heF9jbG9ja19r aHogJiYgbW9kZS0+Y2xvY2sgPiBkcGktPmNvbmYtPm1heF9jbG9ja19raHopDQorCQlyZXR1cm4g TU9ERV9DTE9DS19ISUdIOw0KKw0KKwlyZXR1cm4gTU9ERV9PSzsNCit9DQorDQogc3RhdGljIGNv bnN0IHN0cnVjdCBkcm1fYnJpZGdlX2Z1bmNzIG10a19kcGlfYnJpZGdlX2Z1bmNzID0gew0KIAku YXR0YWNoID0gbXRrX2RwaV9icmlkZ2VfYXR0YWNoLA0KIAkubW9kZV9zZXQgPSBtdGtfZHBpX2Jy aWRnZV9tb2RlX3NldCwNCisJLm1vZGVfdmFsaWQgPSBtdGtfZHBpX2JyaWRnZV9tb2RlX3ZhbGlk LA0KIAkuZGlzYWJsZSA9IG10a19kcGlfYnJpZGdlX2Rpc2FibGUsDQogCS5lbmFibGUgPSBtdGtf ZHBpX2JyaWRnZV9lbmFibGUsDQogfTsNCkBAIC02NzMsMTcgKzY4NywyMCBAQCBzdGF0aWMgdW5z aWduZWQgaW50IG10ODE4M19jYWxjdWxhdGVfZmFjdG9yKGludCBjbG9jaykNCiBzdGF0aWMgY29u c3Qgc3RydWN0IG10a19kcGlfY29uZiBtdDgxNzNfY29uZiA9IHsNCiAJLmNhbF9mYWN0b3IgPSBt dDgxNzNfY2FsY3VsYXRlX2ZhY3RvciwNCiAJLnJlZ19oX2ZyZV9jb24gPSAweGUwLA0KKwkubWF4 X2Nsb2NrX2toeiA9IDMwMDAwMCwNCiB9Ow0KIA0KIHN0YXRpYyBjb25zdCBzdHJ1Y3QgbXRrX2Rw aV9jb25mIG10MjcwMV9jb25mID0gew0KIAkuY2FsX2ZhY3RvciA9IG10MjcwMV9jYWxjdWxhdGVf ZmFjdG9yLA0KIAkucmVnX2hfZnJlX2NvbiA9IDB4YjAsDQogCS5lZGdlX3NlbF9lbiA9IHRydWUs DQorCS5tYXhfY2xvY2tfa2h6ID0gMTUwMDAwLA0KIH07DQogDQogc3RhdGljIGNvbnN0IHN0cnVj dCBtdGtfZHBpX2NvbmYgbXQ4MTgzX2NvbmYgPSB7DQogCS5jYWxfZmFjdG9yID0gbXQ4MTgzX2Nh bGN1bGF0ZV9mYWN0b3IsDQogCS5yZWdfaF9mcmVfY29uID0gMHhlMCwNCisJLm1heF9jbG9ja19r aHogPSAxMDAwMDAsDQogfTsNCiANCiBzdGF0aWMgaW50IG10a19kcGlfcHJvYmUoc3RydWN0IHBs YXRmb3JtX2RldmljZSAqcGRldikNCi0tIA0KMi4yNS4xDQo=