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From:   Andy Lutomirski <luto@amacapital.net>
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Subject: Re: [GIT PULL] x86/urgent for v5.11-rc7
Date:   Sun, 7 Feb 2021 10:31:32 -0800
Message-Id: <2BFAADF3-EBAA-46D6-B1F6-7A41CB85DA1C@amacapital.net>
References: <661b9809-2c6a-5fc8-163b-a159b84c9ab8@intel.com>
Cc:     Borislav Petkov <bp@suse.de>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        Steven Rostedt <rostedt@goodmis.org>, x86-ml <x86@kernel.org>,
        lkml <linux-kernel@vger.kernel.org>
In-Reply-To: <661b9809-2c6a-5fc8-163b-a159b84c9ab8@intel.com>
To:     Dave Hansen <dave.hansen@intel.com>
Precedence: bulk


> On Feb 7, 2021, at 10:19 AM, Dave Hansen <dave.hansen@intel.com> wrote:
>=20
> =EF=BB=BFOn 2/7/21 9:58 AM, Borislav Petkov wrote:
>>> On Sun, Feb 07, 2021 at 09:49:18AM -0800, Linus Torvalds wrote:
>>> On Sun, Feb 7, 2021 at 2:40 AM Borislav Petkov <bp@suse.de> wrote:
>>>> - Disable CET instrumentation in the kernel so that gcc doesn't add
>>>> ENDBR64 to kernel code and thus confuse tracing.
>>> So this is clearly the right thing to do for now, but I wonder if
>>> people have a plan for actually enabling CET and endbr at cpl0 at some
>>> point?
>> It probably is an item on some Intel manager's to-enable list. So far,
>> the CET enablement concentrates only on userspace but dhansen might know
>> more about future plans. CCed.
>=20
> It's definitely on our radar to look at after CET userspace.
>=20
> The only question for me is whether it will be worth doing with the
> exiting kernel entry/exit architecture.

I assume you mean: is anyone sufficiently inspired to try to handle NMI corr=
ectly?  I have a whole pile of nacks saved up for incorrect implementations,=
 although I will try to wrap them in polite explanations of precisely what i=
s wrong :)

(I=E2=80=99ve contemplated doing this myself, and it doesn=E2=80=99t sound f=
un at all.)=