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Date:   Mon, 08 Feb 2021 11:59:07 +0000
From:   Marc Zyngier <maz@kernel.org>
To:     Luo Jiaxing <luojiaxing@huawei.com>
Cc:     linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
        linuxarm@openeuler.org
Subject: Re: [PATCH v1 1/2] irqchip/gic-v3-its: don't set bitmap for LPI which
 user didn't allocate
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 <1612781926-56206-2-git-send-email-luojiaxing@huawei.com>
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On 2021-02-08 10:58, Luo Jiaxing wrote:
> The driver sets the LPI bitmap of device based on 
> get_count_order(nvecs).
> This means that when the number of LPI interrupts does not meet the 
> power
> of two, redundant bits are set in the LPI bitmap. However, when free
> interrupt, these redundant bits is not cleared. As a result, device 
> will
> fails to allocate the same numbers of interrupts next time.
> 
> Therefore, clear the redundant bits set in LPI bitmap.
> 
> Fixes: 4615fbc3788d ("genirq/irqdomain: Don't try to free an interrupt
> that has no mapping")
> 
> Signed-off-by: Luo Jiaxing <luojiaxing@huawei.com>
> ---
>  drivers/irqchip/irq-gic-v3-its.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/irqchip/irq-gic-v3-its.c 
> b/drivers/irqchip/irq-gic-v3-its.c
> index ed46e60..027f7ef 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -3435,6 +3435,10 @@ static int its_alloc_device_irq(struct
> its_device *dev, int nvecs, irq_hw_number
> 
>  	*hwirq = dev->event_map.lpi_base + idx;
> 
> +	bitmap_clear(dev->event_map.lpi_map,
> +		     idx + nvecs,
> +		     roundup_pow_of_two(nvecs) - nvecs);
> +
>  	return 0;
>  }

What makes you think that the remaining LPIs are free to be released?
Even if the end-point has request a non-po2 number of MSIs, it could
very well rely on the the rest of it to be available (specially in the
case of PCI Multi-MSI).

Have a look at the thread pointed out by John for a potential fix.

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...