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Subject: Re: [PATCH v3 0/5] Add APCS support for SDX55
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     viresh.kumar@linaro.org, ulf.hansson@linaro.org,
        bjorn.andersson@linaro.org, agross@kernel.org,
        linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
        Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To:     Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
        jassisinghbrar@gmail.com, mturquette@baylibre.com,
        robh+dt@kernel.org
Date:   Mon, 08 Feb 2021 09:46:11 -0800
Message-ID: <161280637168.76967.9168707371952675235@swboyd.mtv.corp.google.com>
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Quoting Manivannan Sadhasivam (2021-01-17 20:11:51)
> Changes in v2:
>=20
> * Modified the max_register value as per the SDX55 IPC offset in mailbox
>   driver.
>=20
> Manivannan Sadhasivam (5):
>   dt-bindings: mailbox: Add binding for SDX55 APCS
>   mailbox: qcom: Add support for SDX55 APCS IPC

I think I can apply the clk patches to clk tree without the mailbox
patches, right?

>   dt-bindings: clock: Add Qualcomm A7 PLL binding
>   clk: qcom: Add A7 PLL support
>   clk: qcom: Add SDX55 APCS clock controller support
>