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[23.128.96.18]) by mx.google.com with ESMTP id g2si10070510eds.199.2021.02.08.12.28.18; Mon, 08 Feb 2021 12:28:41 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236842AbhBHU1X (ORCPT + 99 others); Mon, 8 Feb 2021 15:27:23 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:56082 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235826AbhBHTEg (ORCPT ); Mon, 8 Feb 2021 14:04:36 -0500 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1l9Bou-004vFh-KW; Mon, 08 Feb 2021 20:03:36 +0100 Date: Mon, 8 Feb 2021 20:03:36 +0100 From: Andrew Lunn To: Serge Semin Cc: Serge Semin , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Jakub Kicinski , Joao Pinto , Jose Abreu , Heiner Kallweit , Russell King , Alexey Malahov , Pavel Parkhomenko , Vyacheslav Mitrofanov , Maxime Coquelin , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 01/20] net: phy: realtek: Fix events detection failure in LPI mode Message-ID: References: <20210208140341.9271-1-Sergey.Semin@baikalelectronics.ru> <20210208140341.9271-2-Sergey.Semin@baikalelectronics.ru> <20210208174441.z4nnugkaadhmgnum@mobilestation> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210208174441.z4nnugkaadhmgnum@mobilestation> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Hi Andrew, > > I honestly tried to find any doc with a glimpse of errata for RTL8211E > PHY, but with no luck. Official datasheet didn't have any info regarding > possible hw bugs too. Thus I had no choice but to find a fix of the > problem myself. > > It took me some time to figure out why the events weren't reported after > the very first link setup (turned out only a full HW reset clears the > PC1R.10 bit state). I thought it could have been connected with some > sleep/idle/power-safe mode. So I disabled the EEE initialization in the > STMMAC driver. It worked. Then I left the EEE mode enabled, but called the > phy_init_eee(phy, 0) method with "clk_stop_enable==0", so PHY wouldn't > stop RXC in LPI mode. And it wonderfully worked. Then I started to dig in > from another side. I left "RXC disable in LPI" mode enabled and tried to > figure out what was going on with the PHY when it stopped reporting events > just by reading from its CSR using phytool utility. It was curious to > discover that any attempt to read from any PHY register caused the problem > disappearance (LED2 started blinking, events got to be reported). Since I > did nothing but a mere reading from a random even EEE-unrelated register I > inferred that the problem must be in some HW/PHY bug. That's how I've got > to the patch introduced here. If you have any better idea what could be a > reason of that weird behavior I'd be glad to test it out on my device. It is a reasonable explanation, and a read should not do any harm. Reviewed-by: Andrew Lunn Andrew