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[23.128.96.18]) by mx.google.com with ESMTP id m23si12526900eds.593.2021.02.08.15.13.52; Mon, 08 Feb 2021 15:14:15 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230049AbhBHXEi (ORCPT + 99 others); Mon, 8 Feb 2021 18:04:38 -0500 Received: from mga11.intel.com ([192.55.52.93]:39580 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229609AbhBHXEc (ORCPT ); Mon, 8 Feb 2021 18:04:32 -0500 IronPort-SDR: uM2xztBP8WqeggSLNW9fPwP7L5HM9d0qFDFdPf0tKGf8TvcT+UYWUi4c3pBoYLAAqXqxVIgl/q hfYneGTf7k5Q== X-IronPort-AV: E=McAfee;i="6000,8403,9889"; a="178284707" X-IronPort-AV: E=Sophos;i="5.81,163,1610438400"; d="scan'208";a="178284707" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2021 15:03:50 -0800 IronPort-SDR: 6GEVXz/VgALvszVbd0TdqgdmvophOiP8mEI+0QbfRkrsOKkVyCH9sNyQbMCxLLxK5UlgBJvyVo O6/xZ0f0qpKg== X-IronPort-AV: E=Sophos;i="5.81,163,1610438400"; d="scan'208";a="358962658" Received: from yyu32-mobl1.amr.corp.intel.com (HELO [10.251.11.33]) ([10.251.11.33]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2021 15:03:48 -0800 Subject: Re: [PATCH v19 08/25] x86/mm: Introduce _PAGE_COW From: "Yu, Yu-cheng" To: Dave Hansen , Kees Cook Cc: x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V. Shankar" , Vedvyas Shanbhogue , Dave Martin , Weijiang Yang , Pengfei Xu References: <20210203225547.32221-1-yu-cheng.yu@intel.com> <20210203225547.32221-9-yu-cheng.yu@intel.com> <202102041215.B54FCA552F@keescook> <2e43bf0b-e1a9-99f6-8d5d-d6e6886b4217@intel.com> <7381d8c1-5e1c-2667-7cb8-0a99f2c79b6d@intel.com> Message-ID: Date: Mon, 8 Feb 2021 15:03:47 -0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.7.0 MIME-Version: 1.0 In-Reply-To: <7381d8c1-5e1c-2667-7cb8-0a99f2c79b6d@intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2/5/2021 10:41 AM, Yu, Yu-cheng wrote: > On 2/4/2021 12:27 PM, Dave Hansen wrote: >> On 2/4/21 12:19 PM, Kees Cook wrote: >>>> (e) A page where the processor observed a Write=1 PTE, started a >>>> write, set >>>>      Dirty=1, but then observed a Write=0 PTE.  That's possible >>>> today, but >>>>      will not happen on processors that support shadow stack. >>> What happens for "e" with/without CET? It sounds like direct writes to >>> such pages will be (correctly) rejected by the MMU? >> >> A page fault would be generated regardless of CET support. >> >> If CET were not around, the fault would be reported as a present, write >> fault. >> >> If this happened and CET were around (which shouldn't happen in >> practice, it means we have a hardware issue) a page fault exception is >> generated. > > Thanks for the clarification.  With or without CET, direct write to > Write=0, Dirty=1 PTE triggers page fault. > >> Yu-cheng, I'm not sure there's enough debugging around to >> tell us if this happens.  Would we even notice? > > That potential hardware issue is, on a CET-capable system, a processor > writes to a Write=1, Dirty=0 page, and then observes the PTE is Write=0, > Dirty=1.  Let me think about it... > One way to detect the potential issue is adding a check when a non-shadow stack page's PTE goes from RW=0 to RW=1, like the following... diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h index 29aa6f07e3c9..241b94a0fa77 100644 --- a/arch/x86/include/asm/pgtable.h +++ b/arch/x86/include/asm/pgtable.h @@ -405,6 +405,8 @@ static inline pte_t pte_mkyoung(pte_t pte) static inline pte_t pte_mkwrite(pte_t pte) { if (cpu_feature_enabled(X86_FEATURE_SHSTK)) { + WARN_ONCE((pte_flags(pte) & (_PAGE_RW | _PAGE_DIRTY)) == + _PAGE_DIRTY, "Found transient shadow stack PTE\n"); if (pte_flags(pte) & _PAGE_COW) { pte = pte_clear_flags(pte, _PAGE_COW); pte = pte_set_flags(pte, _PAGE_DIRTY); I run all my routine stress tests with the changes, and do not see any warning triggered. If this change is desirable, we can probably add #ifdef CONFIG_DEBUG_VM around it and make it a separate patch. -- Yu-cheng