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Date:   Tue, 9 Feb 2021 13:24:43 -0600
From:   Rob Herring <robh@kernel.org>
To:     Suman Anna <s-anna@ti.com>
Cc:     Jassi Brar <jassisinghbrar@gmail.com>, devicetree@vger.kernel.org,
        linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] dt-bindings: mailbox: omap: Update binding for AM64x
 SoCs
Message-ID: <20210209192443.GA4192418@robh.at.kernel.org>
References: <20210127195600.23501-1-s-anna@ti.com>
 <20210127195600.23501-2-s-anna@ti.com>
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On Wed, Jan 27, 2021 at 01:55:59PM -0600, Suman Anna wrote:
> Update the existing OMAP Mailbox binding to include the info for
> AM64x SoCs. There are some minor IP integration differences between
> the AM64x SoCs and the previous AM65x and J721E SoC families.
> 
> Signed-off-by: Suman Anna <s-anna@ti.com>
> ---
>  .../bindings/mailbox/omap-mailbox.txt         | 22 +++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
> index 5fe80c1c19fc..c993d1a5c14a 100644
> --- a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
> +++ b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
> @@ -28,6 +28,9 @@ SoCs has each of these instances form a cluster and combine multiple clusters
>  into a single IP block present within the Main NavSS. The interrupt lines from
>  all these clusters are multiplexed and routed to different processor subsystems
>  over a limited number of common interrupt output lines of an Interrupt Router.
> +The AM64x SoCS also uses a single IP block comprising of multiple clusters,
> +but the number of clusters are smaller, and the interrupt output lines are
> +connected directly to various processors.
>  
>  Mailbox Device Node:
>  ====================
> @@ -42,6 +45,7 @@ Required properties:
>  			    "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
>  						   AM43xx and DRA7xx SoCs
>  			    "ti,am654-mailbox" for K3 AM65x and J721E SoCs
> +			    "ti,am64-mailbox" for K3 AM64x SoCs
>  - reg:			Contains the mailbox register address range (base
>  			address and length)
>  - interrupts:		Contains the interrupt information for the mailbox
> @@ -178,3 +182,21 @@ mailbox: mailbox@480c8000 {
>  		};
>  	};
>  };
> +
> +4. /* AM64x */
> +&cbass_main {

Please don't add examples for just a new compatible.

> +	mailbox0_cluster2: mailbox@29020000 {
> +		compatible = "ti,am64-mailbox";
> +		reg = <0x00 0x29020000 0x00 0x200>;
> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
> +		             <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +		#mbox-cells = <1>;
> +		ti,mbox-num-users = <4>;
> +		ti,mbox-num-fifos = <16>;
> +
> +		mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
> +			ti,mbox-rx = <0 0 2>;
> +			ti,mbox-tx = <1 0 2>;
> +		};
> +	};
> +};
> -- 
> 2.29.2
>