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From:   Marcin Wojtas <mw@semihalf.com>
Date:   Wed, 10 Feb 2021 15:02:00 +0100
Message-ID: <CAPv3WKfs3mYsM5omSSF+yZjo_s8-qFh9Yrr8JqB8FpvmPSvWdQ@mail.gmail.com>
Subject: Re: [PATCH v5 4/5] dts: marvell: Enable 10G interfaces on 9130-DB and
 9131-DB boards
To:     Kostya Porotchkin <kostap@marvell.com>
Cc:     Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        Vladimir Vid <vladimir.vid@sartura.hr>, tmn505@gmail.com,
        luka.kovacic@sartura.hr,
        Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
        =?UTF-8?Q?Gr=C3=A9gory_Clement?= <gregory.clement@bootlin.com>,
        Andrew Lunn <andrew@lunn.ch>, Rob Herring <robh+dt@kernel.org>,
        vkoul@kernel.org, kishon@ti.com,
        =?UTF-8?Q?Miqu=C3=A8l_Raynal?= <miquel.raynal@bootlin.com>,
        Grzegorz Jaszczyk <jaz@semihalf.com>, nadavh@marvell.com,
        Stefan Chulski <stefanc@marvell.com>,
        =?UTF-8?B?QmVuIFBlbGVkICjXkdefINek15zXkyk=?= <bpeled@marvell.com>
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=C5=9Br., 10 lut 2021 o 14:16 <kostap@marvell.com> napisa=C5=82(a):
>
> From: Stefan Chulski <stefanc@marvell.com>
>
> This patch enables eth0 10G interface on CN9130-DB paltforms and
> eth0 10G and eth3 10G interfaces on CN9131-DB.

Thank you.
Reviewed-by: Marcin Wojtas <mw@semihalf.com>

>
> Signed-off-by: Stefan Chulski <stefanc@marvell.com>
> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
> ---
>  arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 2 +-
>  arch/arm64/boot/dts/marvell/cn9131-db.dtsi | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot=
/dts/marvell/cn9130-db.dtsi
> index 8de3a552b806..97c74b81fd78 100644
> --- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
> +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
> @@ -125,7 +125,7 @@
>
>  /* SLM-1521-V2, CON9 */
>  &cp0_eth0 {
> -       status =3D "disabled";
> +       status =3D "okay";
>         phy-mode =3D "10gbase-kr";
>         /* Generic PHY, providing serdes lanes */
>         phys =3D <&cp0_comphy4 0>;
> diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi b/arch/arm64/boot=
/dts/marvell/cn9131-db.dtsi
> index 82471a83ad6d..f2e4d3a6a4f8 100644
> --- a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
> +++ b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
> @@ -84,7 +84,7 @@
>
>  /* CON50 */
>  &cp1_eth0 {
> -       status =3D "disabled";
> +       status =3D "okay";
>         phy-mode =3D "10gbase-kr";
>         /* Generic PHY, providing serdes lanes */
>         phys =3D <&cp1_comphy4 0>;
> --
> 2.17.1
>