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Subject: Re: [PATCH v5 0/4] perf vendor events: Support PMU events for A64FX
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From:   John Garry <john.garry@huawei.com>
Message-ID: <ae8b6d89-5fcd-bff6-6d4d-bb350dca38fe@huawei.com>
Date:   Wed, 10 Feb 2021 15:48:09 +0000
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On 10/02/2021 15:34, nakamura.shun@fujitsu.com wrote:
> Hi, John
> 
>> So my series is now on remotes/origin/tmp.perf/core in Arnaldo's acme git, so
> 
>> you could resend against that.
> 
>> 
> 
>> https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git
> 
>> 
> 
>> Or again, put my series on perf/core and send against that.
> 
> I will resend based on tmp.perf/core.

Actually it is now on perf/core, so that is a better baseline.

> 
>> As for patch 3/4, firstly I'd say that it is not a 'fix'. As well, please ensure it causes
> 
>> no regression on x86 or arm64. So like "perf list" output is same as before (with
> 
>> just that change), and also test some same perf events and metrics (x86 only) to
> 
>> ensure that they are ok.
> 
>> Please also ensure no regression on "perf test".
> 
> I will fix the subject of patch 3/4.
> 
> I have checked the following:
> 
> - perf list does not change for x86 and A64FX
> 
> - No regression on perf test
> 
> - No problem with FLOPs and PMU event counters on x86
> 
>> BTW, please config your mail client for no text encoding.
> 
> I will send it in HTML format.

Hmmm, that's not better. I think that the mail servers reject html.

Please consult Documentation/process/email-clients.rst

Thanks,
John