Received: by 2002:a05:6a10:8c0a:0:0:0:0 with SMTP id go10csp1698114pxb; Wed, 10 Feb 2021 14:42:25 -0800 (PST) X-Google-Smtp-Source: ABdhPJwOFUXeAUgM0oqas/KUJyJig9b1FdFIuRvjRF9V5Go4Aia4bjy3+NSM3t2RxK6tFprjCaSL X-Received: by 2002:a17:906:d8ae:: with SMTP id qc14mr5271518ejb.129.1612996945046; Wed, 10 Feb 2021 14:42:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612996945; cv=none; d=google.com; s=arc-20160816; b=nI2ceifQlsjbbXfqgCVKPwlJ9h4VF9OZ9weTYxXG6nCEP2uVX2HIUlMrcLIjWRiXUw FtoIo2pIdVpoZuIJzDoeWf44saad6LxBs5+UaqLlfq8/AztrNs6AZU3ErUn3t3hM1yxV FmdYj3sIFXgaN1eRyXHpZ1f4zelOs9utrX2lhr1ZzjAxltv5H1/VLK+CpQkLUOmO9au3 2/pg10sssioZm8GCe57ZkmIYb8KTDbxvMRpOl4y7kzz4FprToOd8fNMNaKoCrHfQjxEK RYnKlyfGLKbZPGch+HszprPO5zD1k0UgsZc5phyPMZjMkNYOdtAz4aerypUQLbStiWW1 LWGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:message-id:in-reply-to :subject:cc:to:from:date; bh=VCofjB0wyqDxx9dLlu2dmr3hNh8F1KakMXPVoE0UrbM=; b=SgpmrOTPKkW3WqwD1TldCUTCOvnDv/QTrvBOKB18h7dtSr0o6PajEbAIxkBnCRgSow VhJIqVgxxkafVirPZ/uZig5P9uN0xtcS5W+IQlAyCYxqAHNa+THfVutFJ331NhRXRM5F imDC3wTV+b8bU4PjREsx0nVZeV3nP+6+Tl8wHAz8POigTdAS6HiHPcnOWpakeeV87i8/ xBciX3/jLsYpFtEgF83K3z5VH6vFIaHNzKBq7OFIBs2jSaIB5ged+t+0dcOi3aoVA1gv y5rlnOAdhZs11T/Js5BfEjqY1ch9IODnnhE+3IaRJDA2GIIBCxQ+Al48vbDsXcZFFpo1 pA3Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id 4si2769070edc.221.2021.02.10.14.41.58; Wed, 10 Feb 2021 14:42:25 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233189AbhBJWg5 (ORCPT + 99 others); Wed, 10 Feb 2021 17:36:57 -0500 Received: from kvm5.telegraphics.com.au ([98.124.60.144]:44078 "EHLO kvm5.telegraphics.com.au" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233733AbhBJWgL (ORCPT ); Wed, 10 Feb 2021 17:36:11 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by kvm5.telegraphics.com.au (Postfix) with ESMTP id 8CBF62A94E; Wed, 10 Feb 2021 17:34:46 -0500 (EST) Date: Thu, 11 Feb 2021 09:34:51 +1100 (AEDT) From: Finn Thain To: "Song Bao Hua (Barry Song)" cc: tanxiaofei , "jejb@linux.ibm.com" , "martin.petersen@oracle.com" , "linux-scsi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linuxarm@openeuler.org" , "linux-m68k@vger.kernel.org" Subject: RE: [Linuxarm] Re: [PATCH for-next 00/32] spin lock usage optimization for SCSI drivers In-Reply-To: <13c414b9bd7940caa5e1df810356dcfd@hisilicon.com> Message-ID: <221cb29-53a8-fd1-4232-360655f28f3@telegraphics.com.au> References: <1612697823-8073-1-git-send-email-tanxiaofei@huawei.com> <31cd807d-3d0-ed64-60d-fde32cb3833c@telegraphics.com.au> <88d26bd86c314e5483ec596952054be7@hisilicon.com> <00c06b19e87a425fa3a4b6aaecc66d49@hisilicon.com> <9611728-3e7-3954-cfee-f3d3cf45df6@telegraphics.com.au> <13c414b9bd7940caa5e1df810356dcfd@hisilicon.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="-1463811774-653018509-1612996491=:23" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. ---1463811774-653018509-1612996491=:23 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE On Wed, 10 Feb 2021, Song Bao Hua (Barry Song) wrote: > > On Wed, 10 Feb 2021, Song Bao Hua (Barry Song) wrote: > >=20 > > > > > > > > There is no warning from m68k builds. That's because=20 > > > > arch_irqs_disabled() returns true when the IPL is non-zero. > > > > > > So for m68k, the case is > > > arch_irqs_disabled() is true, but interrupts can still come? > > > > > > Then it seems it is very confusing. If prioritized interrupts can=20 > > > still come while arch_irqs_disabled() is true, > >=20 > > Yes, on m68k CPUs, an IRQ having a priority level higher than the=20 > > present priority mask will get serviced. > >=20 > > Non-Maskable Interrupt (NMI) is not subject to this rule and gets=20 > > serviced regardless. > >=20 > > > how could spin_lock_irqsave() block the prioritized interrupts? > >=20 > > It raises the the mask level to 7. Again, please see=20 > > arch/m68k/include/asm/irqflags.h >=20 > Hi Finn, > Thanks for your explanation again. >=20 > TBH, that is why m68k is so confusing. irqs_disabled() on m68k should=20 > just reflect the status of all interrupts have been disabled except NMI. >=20 > irqs_disabled() should be consistent with the calling of APIs such as=20 > local_irq_disable, local_irq_save, spin_lock_irqsave etc. >=20 When irqs_disabled() returns true, we cannot infer that=20 arch_local_irq_disable() was called. But I have not yet found driver code= =20 or core kernel code attempting that inference. > >=20 > > > Isn't arch_irqs_disabled() a status reflection of irq disable API? > > > > >=20 > > Why not? >=20 > If so, arch_irqs_disabled() should mean all interrupts have been masked= =20 > except NMI as NMI is unmaskable. >=20 Can you support that claim with a reference to core kernel code or=20 documentation? (If some arch code agrees with you, that's neither here nor= =20 there.) > >=20 > > Are all interrupts (including NMI) masked whenever=20 > > arch_irqs_disabled() returns true on your platforms? >=20 > On my platform, once irqs_disabled() is true, all interrupts are masked= =20 > except NMI. NMI just ignore spin_lock_irqsave or local_irq_disable. >=20 > On ARM64, we also have high-priority interrupts, but they are running as > PESUDO_NMI: > https://lwn.net/Articles/755906/ >=20 A glance at the ARM GIC specification suggests that your hardware works=20 much like 68000 hardware. When enabled, a CPU interface takes the highest priority pending=20 interrupt for its connected processor and determines whether the=20 interrupt has sufficient priority for it to signal the interrupt=20 request to the processor. [...] When the processor acknowledges the interrupt at the CPU interface, the= =20 Distributor changes the status of the interrupt from pending to either= =20 active, or active and pending. At this point the CPU interface can=20 signal another interrupt to the processor, to preempt interrupts that=20 are active on the processor. If there is no pending interrupt with=20 sufficient priority for signaling to the processor, the interface=20 deasserts the interrupt request signal to the processor. https://developer.arm.com/documentation/ihi0048/b/ Have you considered that Linux/arm might benefit if it could fully exploit= =20 hardware features already available, such as the interrupt priority=20 masking feature in the GIC in existing arm systems? > On m68k, it seems you mean=EF=BC=9A > irq_disabled() is true, but high-priority interrupts can still come; > local_irq_disable() can disable high-priority interrupts, and at that > time, irq_disabled() is also true. >=20 > TBH, this is wrong and confusing on m68k. >=20 Like you, I was surprised when I learned about it. But that doesn't mean=20 it's wrong. The fact that it works should tell you something. Things could always be made simpler. But discarding features isn't=20 necessarily an improvement. > >=20 > > > Thanks > > > Barry > > > >=20 > Thanks > Barry >=20 ---1463811774-653018509-1612996491=:23--