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Subject: Re: [PATCH v2 3/3] fpga: versal-fpga: Add versal fpga manager driver
To:     Nava kishore Manne <nava.manne@xilinx.com>, mdf@kernel.org,
        trix@redhat.com, robh+dt@kernel.org, michal.simek@xilinx.com,
        linux-fpga@vger.kernel.org, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        chinnikishore369@gmail.com
Cc:     git@xilinx.com,
        Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
References: <20210211060532.23662-1-nava.manne@xilinx.com>
 <20210211060532.23662-4-nava.manne@xilinx.com>
From:   Randy Dunlap <rdunlap@infradead.org>
Message-ID: <7016de66-f254-2bd6-ce29-3b44133feaa0@infradead.org>
Date:   Wed, 10 Feb 2021 22:23:44 -0800
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Hi--

On 2/10/21 10:05 PM, Nava kishore Manne wrote:
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index bf85b9a65ec2..dcd2ed5a7956 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -223,4 +223,12 @@ config FPGA_MGR_ZYNQMP_FPGA
>  	  to configure the programmable logic(PL) through PS
>  	  on ZynqMP SoC.
>  
> +config FPGA_MGR_VERSAL_FPGA
> +        tristate "Xilinx Versal FPGA"
> +        depends on ARCH_ZYNQMP || COMPILE_TEST
> +        help
> +          Select this option to enable FPGA manager driver support for
> +          Xilinx Versal SOC. This driver uses the versal soc firmware

How about consistently capitalizing Versal and SOC (above and below)?

> +          interface to load programmable logic(PL) images
> +          on versal soc.
>  endif # FPGA


thanks.
-- 
~Randy