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[23.128.96.18]) by mx.google.com with ESMTP id e9si3531746eja.73.2021.02.11.03.06.10; Thu, 11 Feb 2021 03:06:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0220 header.b=ivjzpQOu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=REJECT dis=NONE) header.from=marvell.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231490AbhBKLDL (ORCPT + 99 others); Thu, 11 Feb 2021 06:03:11 -0500 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:57100 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230213AbhBKKuV (ORCPT ); Thu, 11 Feb 2021 05:50:21 -0500 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 11BAj1Ej008594; Thu, 11 Feb 2021 02:49:30 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=PZMQI6qrDBXVkYRESL4+mOJLgJYdSMTv37arfL6XHfc=; b=ivjzpQOubA02toA6Wnrc2n79d/ogk6bvWRr2SYbh4U5S+0sTfQ8N5L1Eb4gUgYXi3vK6 +ORhcJK3ALW4nPj404xm+S3h+bXZhNfP51Hp91m2d1IoA3DL/HmBrRVoWky/2PQuLe+g xao1GHv2Jz7wJCXJRaCY/bqNY4hp1kVXc9Kzt4JgwqfW0Eq5Osp2X4wTVJFSaPb4wQnz h6vwYqVDMJ1JjrmyrK1ckwloPm2+e7YrEFuU8FMGhefQjcYoY/dF9z9oETQ2SNSXT+xP R1IVvzbhQvhd8nVA0Vs5f1tFIKbIRkJ1ecmvJJX/S3xvBbEiZa2uAUMAPZCwSqw23r5h pA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 36hugqef6x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 11 Feb 2021 02:49:30 -0800 Received: from SC-EXCH02.marvell.com (10.93.176.82) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 11 Feb 2021 02:49:28 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 11 Feb 2021 02:49:28 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 11 Feb 2021 02:49:27 -0800 Received: from stefan-pc.marvell.com (stefan-pc.marvell.com [10.5.25.21]) by maili.marvell.com (Postfix) with ESMTP id DA8043F703F; Thu, 11 Feb 2021 02:49:23 -0800 (PST) From: To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH v13 net-next 01/15] doc: marvell: add CM3 address space and PPv2.3 description Date: Thu, 11 Feb 2021 12:48:48 +0200 Message-ID: <1613040542-16500-2-git-send-email-stefanc@marvell.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1613040542-16500-1-git-send-email-stefanc@marvell.com> References: <1613040542-16500-1-git-send-email-stefanc@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369,18.0.737 definitions=2021-02-11_05:2021-02-10,2021-02-11 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Stefan Chulski Patch adds CM3 address space and PPv2.3 description. Signed-off-by: Stefan Chulski Acked-by: Marcin Wojtas --- Documentation/devicetree/bindings/net/marvell-pp2.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/marvell-pp2.txt b/Documentation/devicetree/bindings/net/marvell-pp2.txt index b783976..ce15c17 100644 --- a/Documentation/devicetree/bindings/net/marvell-pp2.txt +++ b/Documentation/devicetree/bindings/net/marvell-pp2.txt @@ -1,5 +1,6 @@ * Marvell Armada 375 Ethernet Controller (PPv2.1) Marvell Armada 7K/8K Ethernet Controller (PPv2.2) + Marvell CN913X Ethernet Controller (PPv2.3) Required properties: @@ -12,10 +13,11 @@ Required properties: - common controller registers - LMS registers - one register area per Ethernet port - For "marvell,armada-7k-pp2", must contain the following register + For "marvell,armada-7k-pp2" used by 7K/8K and CN913X, must contain the following register sets: - packet processor registers - networking interfaces registers + - CM3 address space used for TX Flow Control - clocks: pointers to the reference clocks for this device, consequently: - main controller clock (for both armada-375-pp2 and armada-7k-pp2) @@ -81,7 +83,7 @@ Example for marvell,armada-7k-pp2: cpm_ethernet: ethernet@0 { compatible = "marvell,armada-7k-pp22"; - reg = <0x0 0x100000>, <0x129000 0xb000>; + reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>; clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>, <&cpm_syscon0 1 6>, <&cpm_syscon0 1 18>; clock-names = "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_clk"; -- 1.9.1