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Date:   Thu, 11 Feb 2021 14:08:57 +0100
From:   Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kw@linux.com>
To:     Gustavo Pimentel <Gustavo.Pimentel@synopsys.com>
Cc:     dmaengine@vger.kernel.org, linux-pci@vger.kernel.org,
        linux-kernel@vger.kernel.org, Vinod Koul <vkoul@kernel.org>,
        Dan Williams <dan.j.williams@intel.com>,
        Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: [PATCH v5 09/15] dmaengine: dw-edma: Improve the linked list and
 data blocks definition
Message-ID: <YCUsab1NaHxNG7sU@rocinante>
References: <cover.1613034728.git.gustavo.pimentel@synopsys.com>
 <52812d20d0624b36b92785517b2b61ae9b6cc1ed.1613034728.git.gustavo.pimentel@synopsys.com>
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Hi Gustavo,

> In the previous implementation the driver assumes that only existed 2
> memory spaces that would be equal distributed amount the write/read
> channels.

What do you think about:

  In the previous implementation the driver assumed that there existed
  only two memory spaces that would equally distribute the amount of
  read/write channels.

> This might not be the case on some other implementations, therefore this
> patches changes this requirement so that each write/read channel has
[...]

Probably "patch" here.

Krzysztof