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Subject: Re: [PATCH for next v1 1/2] gpio: omap: Replace raw_spin_lock_irqsave
 with raw_spin_lock in omap_gpio_irq_handler()
To:     Luo Jiaxing <luojiaxing@huawei.com>, <linus.walleij@linaro.org>,
        <andy.shevchenko@gmail.com>, <andriy.shevchenko@linux.intel.com>,
        <ssantosh@kernel.org>, <khilman@kernel.org>
CC:     <linux-gpio@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linuxarm@openeuler.org>
References: <1612774577-55943-1-git-send-email-luojiaxing@huawei.com>
 <1612774577-55943-2-git-send-email-luojiaxing@huawei.com>
From:   Grygorii Strashko <grygorii.strashko@ti.com>
Message-ID: <fab1e871-08e4-fc71-9dbf-9bcacf18e2e1@ti.com>
Date:   Thu, 11 Feb 2021 20:14:53 +0200
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On 08/02/2021 10:56, Luo Jiaxing wrote:
> There is no need to use API with _irqsave in omap_gpio_irq_handler(),
> because it already be in a irq-disabled context.
> 
> Signed-off-by: Luo Jiaxing <luojiaxing@huawei.com>
> ---
>   drivers/gpio/gpio-omap.c | 15 ++++++---------
>   1 file changed, 6 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index 41952bb..dc8bbf4 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -560,8 +560,6 @@ static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
>   	u32 enabled, isr, edge;
>   	unsigned int bit;
>   	struct gpio_bank *bank = gpiobank;
> -	unsigned long wa_lock_flags;
> -	unsigned long lock_flags;
>   
>   	isr_reg = bank->base + bank->regs->irqstatus;
>   	if (WARN_ON(!isr_reg))
> @@ -572,7 +570,7 @@ static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
>   		return IRQ_NONE;
>   
>   	while (1) {
> -		raw_spin_lock_irqsave(&bank->lock, lock_flags);
> +		raw_spin_lock(&bank->lock);
>   
>   		enabled = omap_get_gpio_irqbank_mask(bank);
>   		isr = readl_relaxed(isr_reg) & enabled;
> @@ -586,7 +584,7 @@ static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
>   		if (edge)
>   			omap_clear_gpio_irqbank(bank, edge);
>   
> -		raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
> +		raw_spin_unlock(&bank->lock);
>   
>   		if (!isr)
>   			break;
> @@ -595,7 +593,7 @@ static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
>   			bit = __ffs(isr);
>   			isr &= ~(BIT(bit));
>   
> -			raw_spin_lock_irqsave(&bank->lock, lock_flags);
> +			raw_spin_lock(&bank->lock);
>   			/*
>   			 * Some chips can't respond to both rising and falling
>   			 * at the same time.  If this irq was requested with
> @@ -606,15 +604,14 @@ static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
>   			if (bank->toggle_mask & (BIT(bit)))
>   				omap_toggle_gpio_edge_triggering(bank, bit);
>   
> -			raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
> +			raw_spin_unlock(&bank->lock);
>   
> -			raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
> +			raw_spin_lock(&bank->wa_lock);
>   
>   			generic_handle_irq(irq_find_mapping(bank->chip.irq.domain,
>   							    bit));
>   
> -			raw_spin_unlock_irqrestore(&bank->wa_lock,
> -						   wa_lock_flags);
> +			raw_spin_unlock(&bank->wa_lock);
>   		}
>   	}
>   exit:
> 

NACK.
Who said that this is always hard IRQ handler?
What about RT-kernel or boot with "threadirqs"?

-- 
Best regards,
grygorii